rockbox.git - The Rockbox source code.

Age	Commit message (Expand)	Author	Files	Lines
2020-08-30	jz4760: Prioritize Audio DMA and TCU0 (systick) above all others	Solomon Peachy	1	-31/+13
2020-08-30	jz4760: Revert back to the delay loop udelay()	Solomon Peachy	1	-1/+1
2020-08-29	jz4760: Rework IRQ priorities, make audio the highest.	Solomon Peachy	1	-10/+29
2020-08-29	jz4760: Disable dynamic clocking entirely.	Solomon Peachy	1	-1/+1
2020-08-29	jz4760: do the MSC (ie SD) clocking setup when we change PLL0	Solomon Peachy	1	-6/+4
2020-08-28	jz4760: Pull non-PLL init out of pll0_init() code.	Solomon Peachy	1	-16/+15
2020-08-26	jz4760: fix the new udelay() to use _micro_seconds, not milliseconds	Solomon Peachy	1	-4/+6
2020-08-25	jz4760: Give each SD interface its own DMA channel, semaphore, and mutex	Solomon Peachy	1	-2/+4
2020-08-12	jz4760: Use HW timer for more a more accurate udelay()	Solomon Peachy	1	-0/+29
2020-08-07	jz4760: Support dynamic reclocking!	Solomon Peachy	1	-19/+42
2020-08-07	jz4760: Fixes in PLL calculation and reporting	Solomon Peachy	1	-12/+10
2020-08-07	xduoox3: Set PLL0 to 480MHz, not 492.	Solomon Peachy	1	-1/+1
2020-08-07	jz4760: Don't enable PLL1 until we need audio.	Solomon Peachy	1	-17/+30
2018-07-28	Add cleaned-up xDuoo X3 support	Solomon Peachy	1	-0/+710