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path: root/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
AgeCommit message (Expand)AuthorFilesLines
2020-08-25jz4760: Give each SD interface its own DMA channel, semaphore, and mutexSolomon Peachy1-2/+4
2020-08-12jz4760: Use HW timer for more a more accurate udelay()Solomon Peachy1-0/+29
2020-08-07jz4760: Support dynamic reclocking!Solomon Peachy1-19/+42
2020-08-07jz4760: Fixes in PLL calculation and reportingSolomon Peachy1-12/+10
2020-08-07xduoox3: Set PLL0 to 480MHz, not 492.Solomon Peachy1-1/+1
2020-08-07jz4760: Don't enable PLL1 until we need audio.Solomon Peachy1-17/+30
2018-07-28Add cleaned-up xDuoo X3 supportSolomon Peachy1-0/+710