path: root/firmware/target/mips/mmu-mips.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-28New port: FiiO M3K on bare metalAidan MacDonald1-2/+2
2021-03-04Fix typo in MIPS cache discardAidan MacDonald1-1/+1
2021-03-04mips: Revert to commiting the cache when we're told to discard an unaligned b...Solomon Peachy1-0/+16
2021-03-04Third try fixing MIPS cache codeAidan MacDonald1-14/+1
2021-03-03Really fix the MIPS cache bug this timeAidan MacDonald1-1/+1
2021-03-03Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPSAidan MacDonald1-15/+24
2020-09-05mips: Convert 'nop' to 'ssnop' -- for future-proofingSolomon Peachy1-14/+14
2020-09-03mips: Heavily rework DMA & caching codeSolomon Peachy1-63/+122
2020-08-29XduooX3 Sources WS changesWilliam Wilgus1-6/+6
2018-07-28Add cleaned-up xDuoo X3 supportSolomon Peachy1-59/+49
2011-12-17Commit to certain names for cache coherency APIs and discard the aliases.Michael Sevakis1-6/+0
2011-02-02Clean up multiple definitions of RAM size. Remove -DMEM (make) and MEM (code)...Andree Buschmann1-1/+1
2010-09-09Also rename cpucache_invalidate() function for mips. There's more in the targ...Thomas Martitz1-1/+2
2009-06-04Fix RoLo on MIPS targetsMaurus Cuelenaere1-0/+1
2009-02-13Onda VX747:Maurus Cuelenaere1-1/+91
2009-02-04MIPS:Maurus Cuelenaere1-5/+6
2009-01-21Onda VX747:Maurus Cuelenaere1-0/+125