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mmu-mips.c
Age
Commit message (
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Author
Files
Lines
2021-03-28
New port: FiiO M3K on bare metal
Aidan MacDonald
1
-2
/
+2
2021-03-04
Fix typo in MIPS cache discard
Aidan MacDonald
1
-1
/
+1
2021-03-04
mips: Revert to commiting the cache when we're told to discard an unaligned b...
Solomon Peachy
1
-0
/
+16
2021-03-04
Third try fixing MIPS cache code
Aidan MacDonald
1
-14
/
+1
2021-03-03
Really fix the MIPS cache bug this time
Aidan MacDonald
1
-1
/
+1
2021-03-03
Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPS
Aidan MacDonald
1
-15
/
+24
2020-09-05
mips: Convert 'nop' to 'ssnop' -- for future-proofing
Solomon Peachy
1
-14
/
+14
2020-09-03
mips: Heavily rework DMA & caching code
Solomon Peachy
1
-63
/
+122
2020-08-29
XduooX3 Sources WS changes
William Wilgus
1
-6
/
+6
2018-07-28
Add cleaned-up xDuoo X3 support
Solomon Peachy
1
-59
/
+49
2011-12-17
Commit to certain names for cache coherency APIs and discard the aliases.
Michael Sevakis
1
-6
/
+0
2011-02-02
Clean up multiple definitions of RAM size. Remove -DMEM (make) and MEM (code)...
Andree Buschmann
1
-1
/
+1
2010-09-09
Also rename cpucache_invalidate() function for mips. There's more in the targ...
Thomas Martitz
1
-1
/
+2
2009-06-04
Fix RoLo on MIPS targets
Maurus Cuelenaere
1
-0
/
+1
2009-02-13
Onda VX747:
Maurus Cuelenaere
1
-1
/
+91
2009-02-04
MIPS:
Maurus Cuelenaere
1
-5
/
+6
2009-01-21
Onda VX747:
Maurus Cuelenaere
1
-0
/
+125