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Can be disabled at runtime by setting hold switch.
Boosts sysbench sequential write performance by 34-58%
Change-Id: I060c9d7dddc1b448f18aa46af8f8aff046e07843
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Allow Lineout to behave like headphone port in regards to
plug/unplug pause/resume
Change-Id: I9cb2c9c40e0bdf3bf7e1e272164acd343f6b3850
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* DMA Bulk IN (ie our TX) results in sequential transfers 33-68% faster.
* DMA Bulk OUT (ie RX) is mostly stripped out due to complete brokenness.
* Interrupt and control endpoints remain PIO-driven.
Other improvements:
1) Use consistent endpoint references (no magic numbers)
2) Greatly enhanced logging
3) DMA support can be compiled out completely
4) Setting lockswitch will disable all DMA operations at runtime
5) Much more robust error checking and recovery
Change-Id: I57b82e655e55ced0dfe289e379b0b61d8fe443b4
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Change-Id: I9caf55c1249625dff7e437158afd20a526fa7499
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Speachy suggested we don't shut down the adc on ROLO
this fixes the random adc drop out on ROLO
Change-Id: Ife7d679ce51a6f767963210ee650815f1de12223
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Fixes deficiencies with the button system on the X3
The x3 has an interesting button layout.
Multiple key presses are NOT supported unless
[BUTTON_POWER] is one of the combined keys
As you can imagine this causes problems as the power button takes
precedence in the button system and initiates a shutdown if the
key is held too long
instead of BUTTON_POWER use BUTTON_PWRALT in combination with other keys
IF using as a prerequsite button then BUTTON_POWER should be used
Multiple buttons are emulated by button_read_device but there are a few
caveats to be aware of:
Button Order Matters!
different keys have different priorities, higher priority keys 'overide'
the lower priority keys
VOLUP[7] VOLDN[6] PREV[5] NEXT[4] PLAY[3] OPTION[2] HOME[1]
There will be no true release or repeat events, the user can let off the
button pressed initially and it will still continue to appear to be
pressed as long as the second key is held
Tree scrolling is PLAY+NEXT or PLAY+PREV
Change-Id: I88dfee1c70a6a99659e8227f5becacc50cc43910
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Group commands for a bit more speed
bitdelay was not being inlined
lower bitdelay to 12 cycles
Clean-up magic numbers
Change-Id: Ifeb57a5532807a598f1ec5e1c55f03e4aa1e133f
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Fix issue with first battery sample taking 30 seconds
Clean up code
Change-Id: If2437d241e0ab4e3d23b141f5d853b6cf3209b07
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Change-Id: I591b4f023776b3501fce03e08bfc87a355f4c69b
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Change-Id: Ic31267a2ae82beede72100c1cc5ddf7211aa0abe
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Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
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* Increase audio buffer size to better handle IRQ latency (256->2048)
* Ensure DMA engine is idle prior to starting transfers
* Set AIC to repeat last sample in case of underflows
Change-Id: I9c45c20481ee072e5882b7586fb7d50bd8ef2f35
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Change-Id: I76eda59a391a408d1a6642497d8cc4aeb93a0da1
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Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.
Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
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only check button values with adc when buttons are actually pressed
battery level check frequency is now around 30 seconds
switched to polling for the battery voltage w/ timeout
Ifdef functions Allow BACK OPTION PLAY to be the first of a two key combo
Change-Id: Icb48d62ac8d82b4dc931df5e1c5b4a84a9a69772
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We don't use it on the X3. Should we ever get another jz4760 target
we can revisit this.
Change-Id: I591d02c7e47b35424b3c96b776b31a38e3c8ceee
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Change-Id: If2261aed464fcbe3ea1f036dd18376fa8ff42e69
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halves cpu usage
Change-Id: I3797b01ecd2f7615acfed53a77d8a1f51e947c8b
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add scrolling for clocks and such
moved to a switch based structure.. this ends up a lot cleaner
Change-Id: I940506c4b8dc73f0b776d20810780527cbf7e0d4
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Change-Id: I3e7bc7ffb8d6d0c5d18a6ab38b1a270559a62fb9
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Change-Id: I0c2df20a8c87f7a5bdf25d59904d32806171a544
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Change-Id: I1a84cf28f8a3416d661a8e2e4dd31c9e86f50ba0
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Change-Id: I6ca9f005e412240235354b9369bcc3f4a4ad256f
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Change-Id: Ia2f2dba4a263c82aebc7fab9da4ad69ef90565ea
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(Bootloader uses UART1, and leaves it running when it hands it off to us)
Change-Id: Icde1d713574582f18e9f91b5c95f3917fe324b74
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Change-Id: Ic5ee9e700a0c8acffc39b51cedc24ff44d230fd3
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Change-Id: Ibbbcd9fd1e7e2cfa896678cccaa00296c86c2c62
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(And loop in the IRQ handler to make sure we catch everything!)
Change-Id: I813272c69e981fdc214ec28448ced403ad366ea0
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... the timer-based version used the same timer as our os tick!
Change-Id: Id84b308bfa1145cb8806e1029f2ca26159fb71e1
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(it was effectively the _lowest_ prior to this. wtf?)
Change-Id: I6905c5ba0d87a5e14aeae5d5b79f8f515ac5b806
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Back off to 480MHz [max] clock, bus/mem clock of 120MHz.
576 is unstable on at least one unit, and 528 still glitches.
Change-Id: I020e48532524e739f3bfa42bed570381ccd34959
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Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007
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Adds contrast setting which actually sets the drive voltage
Change-Id: I173238e2efe9e50c6ef4cda9bf991e7ee5568ff5
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Change-Id: Ia17b1d7069af507c3f029bcaed0f65e7e97df275
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(same fix as g#2703 for the jz4760)
Change-Id: Ic6467d9e6085e3057528b6d1a08b7c07e9dceab4
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when timer_set_period is called timer is stopped but never reenabled
Change-Id: I5cfc7a2d5620ff998005e013952b25f1e0a52754
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So it only gets called once, at system startup.
Change-Id: I4c191519009e80dfb118065391295c88a014d25a
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greylib on the xduoo x3 now matches the rest of the 1bit targets
Change-Id: I2685869da6734404356552cc9f4ed5f59ebd6650
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There is no way to detect this at runtime so it is a user setting
Change-Id: Ibc5b87312238c59e3678d512af27e3a3bcb9a58a
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Change-Id: I4877b1c8e4a95259b5ade126e28458b65fbd3c4b
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(Brand new unit lasted one minute shy of 12 hours!)
Change-Id: I0330f43065412d432a45b555bb310f943eb526e7
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* Don't stop clock before switching speeds
* Don't stop clock prior to transactions
* Stop clock at the end of transactions
Will result in slightly better performance and some power saving when
we're not actively using the SD peripheral.
Change-Id: I1c82476cad97137b1469900645ecf7bb0887119a
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* Check to see if clock is [not] running prior to [en|dis]abling it
* Stop clock _prior_ to resetting controller
* Stop clock after transaction is completed, not before initiating it
* Use controller's low power mode (disables clocks when idle)
* Fix, and enable, interrupt-driven DMA transfers
* Fixes for full interrupt-driven operation (WIP, still broken)
Change-Id: I723ffa6450fc85f97898c8a8b3e538ae31c4858e
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There's a code path that calls sd_init_device() while we hold sd_mtx, but
sd_init_device() tries to obtain the mutex while doing its work.
Change-Id: I882c595e9e7cd2224b1db0d413925668628476e9
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* Allows both SD interfaces to have requests in flight simultaneously
* Fixed a deadlock in the hotswap code
* Ensure TX DMA is idle before initiating a request (bug due to a typo)
Change-Id: I988fa29df5f8e41fc6bbdcc517db89842003b34d
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(More specifically, use the SoC's "OS Timer", slaved to the main XTAL so
it doesn't matter how the main CPU is clocked)
Change-Id: I799561ac823ff7f659a05144cf03b6a13d57ea7b
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PLL1 clock for those frequencies has been dropped from 508 to 169.5 MHz,
so it's still a respectable reduction.
(I'm not sure how/why it ever worked with the XTAL source, but it did,
and was off by an audible amount)
Change-Id: I614d87e7dfdfe9210702b9c646d3863c06d6780b
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* for <= 48KHz, BCLK must be 256*freq (ie bdiv = 4)
* for <= 96KHz, BCLK must be 128*freq (ie bdiv = 2)
* for 11/22/44/88 KHz, disable PLL1 and run off XTAL
* cut PLL1 with 12/24/48/98 KHz audio from 516->86MHz
* cut PLL1 with 8/16/32/64 KHz audio from 426->106.5MHz
This should result in significant power savings for
common 44.1KHz audio playback, and pretty good savings
for everything else.
As an added bonus:
* enable de-emphasis filters at 32, 44.1, and 48 KHz
Change-Id: Ie59067cd46c47e62abf4a32c53519efad104d6c8
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default/low speed is 192 MHz, Max is 576
Downclock PCLK/MCLK/etc to 96MHz to save a bit of juice
Honestly the high speed could be dialed down to, eg 384
as this thing is so bloody fast..
Change-Id: Ie65597c74290f1603e65f69dae8e75b59c8ba0b4
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Change-Id: I890c661fbff549de5a224d90e3fbda34c71b3a7e
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