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16 hoursFiiO M3K: disable CPU frequency switchingHEADmasterAidan MacDonald1-20/+0
After conducting some simplistic tests, I found that the power usage did not appear to be affected by the CPU frequency. I tested by playing back a 44.1 KHz FLAC file on single track repeat, and measured current with the AXP173's battery discharge current ADC. The button and LCD backlights were set to always on. Headphones were unplugged and the volume was muted to eliminate any influence from the headphone amp. On average the current usage was between 78-81 mA at 1008 MHz, 252 MHz, and 112 MHz. If anything, 1008 MHz drew _less_ current than the lower frequencies, by about 1-3 mA. A possible explanation for this, assuming it's not just a bias of the test, is that the CPU idle state saves so much power that it's better to maximize the real time that the CPU spends idling. More systematic testing is needed to confirm this. Change-Id: I527473e8c4c12bc1e94f8d4e849fecc108022abe
16 hoursx1000: disable CPU idle stats by defaultAidan MacDonald4-0/+19
There's no point including this in normal builds: the stats are not used for anything, they are not really of interest to anyone except developers, and add a small overhead to the kernel tick. Change-Id: I1b4f67cc62d11d634a8cec279dca513dd10eea96
16 hoursFiiO M3K/X1000: Do system clock initialization in the SPLAidan MacDonald4-39/+45
Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
16 hoursx1000: don't reset all GPIOs at bootAidan MacDonald1-12/+8
What we really want is to avoid any interrupts being generated before the drivers which handle them are properly initialized. Intead of trashing all GPIOs, search for the problem pins and fix them, leaving the others alone. This fixes the M3K's button light flickering on boot and should stop the M3K from entering a potentially confusing "dead" state where all the lights are off but the CPU is still on. Change-Id: I13a6da0f0950190396bff5d6e8c343c668e8fea1
16 hoursx1000: Redesign SPL, and allow it to flash the bootloaderAidan MacDonald5-0/+588
SPL is now designed so core X1000 code is in control of the boot, under the reasonable assumption that the device boots from flash. It should not be too hard to adapt to other X1000 ports. The biggest functional change is that the SPL can now read/write the flash, under the control of a host computer. The SPL relies on the boot ROM for USB communication, so the host has to execute the SPL multiple times following a protocol. Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
9 daysxduoox3: Global volume_limit now applies to the line output as wellSolomon Peachy1-3/+6
The X3's line out is a bit hot, at ~4.3Vpp, so allow it to be backed off. (On my X3, backing it off to -6dB brings Vpp down to ~3.4V) Change-Id: Iea38ef1c6a1b183d0f8fb4eaf2bf9ed6b350a532
9 daysx1000: Trim unused cache functions from the SPL buildAidan MacDonald1-0/+9
Change-Id: Ib645d8ff10cfc672de8ac2debaa17d7dd50dfafb
12 daysx1000: Improve NAND driver APIamachronic4-52/+93
- Proper error codes are now returned from all functions. These codes will be used by a host-side flash tool for error reporting. - nand_erase_block() was replaced by nand_erase_bytes(). The caller can't know how big an eraseblock is with the current API, so next best thing is to verify the correct alignment inside the call and reject the erase if it isn't properly aligned. - Fixed typo in nandcmd_block_erase() which would cause an SFC error to be interpreted as success. Yikes. Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
12 daysx1000: place SPL's NAND bounce buffers in DRAMamachronic2-6/+22
This frees up 2 KiB in the SPL's memory map, leaving more room for code. Change-Id: I01bbe2ab2905b2773a8b76d8c53e9f3d55bd040f
12 daysRemove a duplicate constamachronic1-1/+1
Change-Id: I0e6f4d609eb03155de4cd16aa98cab25f54a6681
2021-03-28New port: FiiO M3K on bare metalAidan MacDonald65-2/+13286
Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
2021-03-27Use STORAGE_NEEDS_BOUNCE_BUFFER instead of STORAGE_NEEDS_ALIGNSolomon Peachy1-0/+1
Enable its use in the jz47xx MIPS targets. (accidently committed g#3249 before making these changes) Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
2021-03-09Move MIPS cache management functions to IRAMAidan MacDonald1-6/+14
Previously these were placed in DRAM, which is overwritten by RoLo when it loads a new image, but RoLo must call commit_discard_idcache() after loading the image. Change-Id: I5dcc4ca711b774166f83c668695edbcabfab2604
2021-03-04Fix typo in MIPS cache discardAidan MacDonald1-1/+1
Change-Id: I6a06e5f3098324d985bd59322755cd68122ec0bf
2021-03-04mips: Revert to commiting the cache when we're told to discard an unaligned ↵Solomon Peachy1-0/+16
block. The filesystem API often passes in unaligned receive buffers, and some code (eg BMP reader) processes data in-place, leading to data loss when we dropped the cache. (And document exactly what we're doing, so we don't go through this again at $future_date) Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
2021-03-04Third try fixing MIPS cache codeAidan MacDonald1-14/+1
Changing this to be a pure discard operation after discussion on IRC Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a
2021-03-03jz4740: Fix incorrect dcache flush in the USB RX DMA code.Solomon Peachy1-2/+0
Change-Id: I01eff581b16569bda97c55afc7adac897b29e0e3
2021-03-03Really fix the MIPS cache bug this timeAidan MacDonald1-1/+1
In fixing the original bug I tried to optimize discard_dcache_range() to minimize writeback and inadvertently introduced a second bug, which typically ends in a TLB refill panic. It occurs only if the range fits within one cache line, and when both the start and end of the range are not aligned to a cache line. This causes ptr to be incremented and end to be decremented, so ptr > end, and the loop can't terminate. Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
2021-03-03Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPSAidan MacDonald2-16/+25
- The range-based cache operations on MIPS were broken and only worked properly when BOTH the address and size were multiples of the cache line size. If this was not the case, the last cache line of the range would not be touched! Fix is to align start/end pointers to cache lines before iterating. - To my knowledge all MIPS processors have a cache, so I enabled HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use the CACHEALIGN_UP/DOWN macros. - Make jz4760/system-target.h define its cache line size properly. Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
2020-11-12pcm: Further cleanup of unused bits of the PCM ACPI:Solomon Peachy2-28/+0
* pcm_get_bytes_remaining() * pcm_calculate_peaks() * pcm_get_peak_buffer() Nothing in-tree uses these at all (except for the lua plugin wrapper) Change-Id: I971b7beed6760250c8b1ce58f401a601e1e2d585
2020-10-31pcm: Get rid of pcm_play_pause() and associated APIsSolomon Peachy2-24/+0
Nothing in the core has used it for some time. It's exported to the plugin API but the last plugins to use it were switched to the mixer API back in 2011. This allows us to get rid of pcm_play_dma_pause() from all audio drivers Change-Id: Ic3fa02592316f84963e41d792d1cabb436d1ff6b
2020-10-15xduoox3: Disable the DAC's digital de-emphasis filter.Solomon Peachy1-5/+1
Whether or not this is correct depends on how the source material was mastered, digitized, and/or encoded. There is no setting appropriate for everything. Eventually I'd like to make this configurable, but I'd want to have it shared with more than one target first. Change-Id: I20a0eff4b3dc2517c33db49d4f72e85bf81d1ca6
2020-10-08Undo the hacks that allowed targets without LEFT/RIGHT (UP/DN) to build.Solomon Peachy2-7/+5
Replaced them with warnings until they are fixed *PROPERLY* Change-Id: I4425200e60f8b5224262a54f105b974cec471d22
2020-10-01xduoox3: Work out clocks for 176/192KHz support.Solomon Peachy1-11/+12
Note: PCM mix buffer sizes are _way_ too small for these high bitrates (We really need to make the mixer stuff use dynamic buffer sizes based on the bitrate. Maybe pre-allocate a max size based on upper bitrate limit, but use only part of it at lower bitrates? So we can have sane latency..) Change-Id: Id7b4afd73dba7f1ffb84b2e1c016859fae5d6835
2020-09-18jz4760: Implement USB DMA RXSolomon Peachy1-22/+135
Can be disabled at runtime by setting hold switch. Boosts sysbench sequential write performance by 34-58% Change-Id: I060c9d7dddc1b448f18aa46af8f8aff046e07843
2020-09-18Headphone / lineout pause/resume #FS13237William Wilgus1-1/+3
Allow Lineout to behave like headphone port in regards to plug/unplug pause/resume Change-Id: I9cb2c9c40e0bdf3bf7e1e272164acd343f6b3850
2020-09-17jz4760: Heavily rework USB driver to add working DMA supportSolomon Peachy2-139/+245
* DMA Bulk IN (ie our TX) results in sequential transfers 33-68% faster. * DMA Bulk OUT (ie RX) is mostly stripped out due to complete brokenness. * Interrupt and control endpoints remain PIO-driven. Other improvements: 1) Use consistent endpoint references (no magic numbers) 2) Greatly enhanced logging 3) DMA support can be compiled out completely 4) Setting lockswitch will disable all DMA operations at runtime 5) Much more robust error checking and recovery Change-Id: I57b82e655e55ced0dfe289e379b0b61d8fe443b4
2020-09-17Xduoo X3 add headphone and lineout status to IO Ports debug menuWilliam Wilgus1-13/+30
Change-Id: I9caf55c1249625dff7e437158afd20a526fa7499
2020-09-13Xduoo X3 no ADC after ROLOWilliam Wilgus1-0/+6
Speachy suggested we don't shut down the adc on ROLO this fixes the random adc drop out on ROLO Change-Id: Ife7d679ce51a6f767963210ee650815f1de12223
2020-09-13Xduoo X3 Add tree scrolling FS#13240, Emulate Multibutton pressesWilliam Wilgus2-19/+50
Fixes deficiencies with the button system on the X3 The x3 has an interesting button layout. Multiple key presses are NOT supported unless [BUTTON_POWER] is one of the combined keys As you can imagine this causes problems as the power button takes precedence in the button system and initiates a shutdown if the key is held too long instead of BUTTON_POWER use BUTTON_PWRALT in combination with other keys IF using as a prerequsite button then BUTTON_POWER should be used Multiple buttons are emulated by button_read_device but there are a few caveats to be aware of: Button Order Matters! different keys have different priorities, higher priority keys 'overide' the lower priority keys VOLUP[7] VOLDN[6] PREV[5] NEXT[4] PLAY[3] OPTION[2] HOME[1] There will be no true release or repeat events, the user can let off the button pressed initially and it will still continue to appear to be pressed as long as the second key is held Tree scrolling is PLAY+NEXT or PLAY+PREV Change-Id: I88dfee1c70a6a99659e8227f5becacc50cc43910
2020-09-08XduooX3 LCD tweaks #2William Wilgus1-48/+110
Group commands for a bit more speed bitdelay was not being inlined lower bitdelay to 12 cycles Clean-up magic numbers Change-Id: Ifeb57a5532807a598f1ec5e1c55f03e4aa1e133f
2020-09-06XduooX3 Gpio reconfigure button system #2William Wilgus1-79/+45
Fix issue with first battery sample taking 30 seconds Clean up code Change-Id: If2437d241e0ab4e3d23b141f5d853b6cf3209b07
2020-09-06jz4760: Fix and re-enable the hardware udelay() timerSolomon Peachy1-12/+19
Change-Id: I591b4f023776b3501fce03e08bfc87a355f4c69b
2020-09-06jz4760: Use a #define for the timer id, not a raw numberSolomon Peachy1-15/+17
Change-Id: Ic31267a2ae82beede72100c1cc5ddf7211aa0abe
2020-09-05mips: Convert 'nop' to 'ssnop' -- for future-proofingSolomon Peachy6-77/+77
Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
2020-09-04jz47xx: Audio path tweaks:Solomon Peachy4-0/+6
* Increase audio buffer size to better handle IRQ latency (256->2048) * Ensure DMA engine is idle prior to starting transfers * Set AIC to repeat last sample in case of underflows Change-Id: I9c45c20481ee072e5882b7586fb7d50bd8ef2f35
2020-09-03Xduoo Gpio fix bugWilliam Wilgus1-0/+3
Change-Id: I76eda59a391a408d1a6642497d8cc4aeb93a0da1
2020-09-03mips: Heavily rework DMA & caching codeSolomon Peachy15-127/+186
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
2020-09-03XduooX3 Gpio reconfigure button systemWilliam Wilgus1-14/+69
only check button values with adc when buttons are actually pressed battery level check frequency is now around 30 seconds switched to polling for the battery voltage w/ timeout Ifdef functions Allow BACK OPTION PLAY to be the first of a two key combo Change-Id: Icb48d62ac8d82b4dc931df5e1c5b4a84a9a69772
2020-09-02jz4760: Dial down PIXCLK as low as possibleSolomon Peachy1-0/+3
We don't use it on the X3. Should we ever get another jz4760 target we can revisit this. Change-Id: I591d02c7e47b35424b3c96b776b31a38e3c8ceee
2020-09-02xduoox3: Disable the LCD and MSC0 clocks as we don't use themSolomon Peachy2-2/+5
Change-Id: If2261aed464fcbe3ea1f036dd18376fa8ff42e69
2020-09-02XduooX3 Slow down greylib framerateWilliam Wilgus1-1/+4
halves cpu usage Change-Id: I3797b01ecd2f7615acfed53a77d8a1f51e947c8b
2020-09-02XduooX3 Debug Menu -- HW_infoWilliam Wilgus1-128/+339
add scrolling for clocks and such moved to a switch based structure.. this ends up a lot cleaner Change-Id: I940506c4b8dc73f0b776d20810780527cbf7e0d4
2020-09-02mips: use .set push/pop in asm codeSolomon Peachy1-2/+5
Change-Id: I3e7bc7ffb8d6d0c5d18a6ab38b1a270559a62fb9
2020-08-31jz4760: use SYSFONT in the hw info debug screen, and restore old fontSolomon Peachy1-1/+2
Change-Id: I0c2df20a8c87f7a5bdf25d59904d32806171a544
2020-08-31Xduoo_x3 Boot Fix red from debug menu changesWilliam Wilgus1-1/+1
Change-Id: I1a84cf28f8a3416d661a8e2e4dd31c9e86f50ba0
2020-08-31xduooX3 debug menu add GPIO IO PortsWilliam Wilgus1-0/+83
Change-Id: I6ca9f005e412240235354b9369bcc3f4a4ad256f
2020-08-30xduoox3: Fix bootloader buildSolomon Peachy1-0/+7
Change-Id: Ia2f2dba4a263c82aebc7fab9da4ad69ef90565ea
2020-08-30jz4760: Explicitly disable UARTs at startupSolomon Peachy3-2/+24
(Bootloader uses UART1, and leaves it running when it hands it off to us) Change-Id: Icde1d713574582f18e9f91b5c95f3917fe324b74
2020-08-30XduooX3 Tweak LCD drive strength and slewWilliam Wilgus1-4/+14
Change-Id: Ic5ee9e700a0c8acffc39b51cedc24ff44d230fd3