From 06c94740e510d0ce04e069f34631a0539e9e6742 Mon Sep 17 00:00:00 2001
From: Amaury Pouly <pamaury@rockbox.org>
Date: Sat, 23 Jul 2011 11:45:18 +0000
Subject: imx233/fuze+: prepare target to enable MMU

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30199 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/export/imx233.h                   | 14 +++++++++-----
 firmware/target/arm/imx233/boot.lds        |  6 +++---
 firmware/target/arm/imx233/system-imx233.c | 27 +++++++++++++++++++--------
 firmware/target/arm/mmu-arm.S              |  4 ++++
 4 files changed, 35 insertions(+), 16 deletions(-)

diff --git a/firmware/export/imx233.h b/firmware/export/imx233.h
index 182442c2ab..682240ac40 100644
--- a/firmware/export/imx233.h
+++ b/firmware/export/imx233.h
@@ -24,12 +24,14 @@
 #define IRAM_ORIG           0
 #define IRAM_SIZE           0x8000
 #define DRAM_ORIG           0x40000000
-#define DRAM_SIZE           0x20000000
+#define DRAM_SIZE           (MEMORYSIZE * 0x100000)
 
-#define TTB_BASE_ADDR (DRAM_ORIG + (MEMORYSIZE*0x100000) - TTB_SIZE)
-#define TTB_SIZE      (0x4000)
-#define TTB_BASE      ((unsigned long *)TTB_BASE_ADDR)
-#define FRAME_SIZE    (240*320*2)
+#define TTB_BASE_ADDR   (IRAM_ORIG + IRAM_SIZE - TTB_SIZE)
+#define TTB_SIZE        0x4000
+#define TTB_BASE        ((unsigned long *)TTB_BASE_ADDR)
+#define FRAME_SIZE      (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
+#define LCD_FRAME_ADDR  (DRAM_ORIG + DRAM_SIZE - FRAME_SIZE)
+#define FRAME           ((unsigned short *)LCD_FRAME_ADDR)
 
 /* USBOTG */
 #define USB_QHARRAY_ATTR    __attribute__((section(".qharray"),nocommon,aligned(2048)))
@@ -48,5 +50,7 @@
 #define __BLOCK_SFTRST  (1 << 31)
 #define __BLOCK_CLKGATE (1 << 30)
 
+#define CACHEALIGN_BITS     4
+
 
 #endif /* __IMX233_H__ */
diff --git a/firmware/target/arm/imx233/boot.lds b/firmware/target/arm/imx233/boot.lds
index cb925b055e..0a8f0ed8f8 100644
--- a/firmware/target/arm/imx233/boot.lds
+++ b/firmware/target/arm/imx233/boot.lds
@@ -8,8 +8,8 @@ STARTUP(target/arm/imx233/crt0.o)
 
 MEMORY
 {
-    IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE
-    DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - TTB_SIZE
+    IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE - TTB_SIZE
+    DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - FRAME_SIZE
 }
 
 SECTIONS
@@ -30,7 +30,7 @@ SECTIONS
     {
         _iramstart = .; // always 0
         *(.vectors)
-        KEEP(*(.vectors));// otherwise there are no reference to it and the linker strip it
+        KEEP(*(.vectors));// otherwise there are no references to it and the linker strip it
         *(.icode)
         *(.irodata)
         *(.idata)
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 58f12506df..c4a32dd46e 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -141,6 +141,25 @@ void imx233_softirq(int src, bool enable)
         __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ;
 }
 
+static void set_page_tables(void)
+{
+    /* map every memory region to itself */
+    map_section(0, 0, 0x1000, CACHE_NONE);
+
+    /* map RAM and enable caching for it */
+    map_section(DRAM_ORIG, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
+    
+    /* enable buffered writing for the framebuffer */
+    map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
+}
+
+void memory_init(void)
+{
+    ttb_init();
+    set_page_tables();
+    enable_mmu();
+}
+
 void system_init(void)
 {
     /* disable all interrupts */
@@ -158,14 +177,6 @@ void system_init(void)
     imx233_timrot_init();
     imx233_dma_init();
     imx233_ssp_init();
-    imx233_i2c_init();
-}
-
-void power_off(void)
-{
-    /* power down */
-    HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD;
-    while(1);
 }
 
 bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S
index 24abfec1a7..39f0edbfce 100644
--- a/firmware/target/arm/mmu-arm.S
+++ b/firmware/target/arm/mmu-arm.S
@@ -44,6 +44,10 @@
 /* MMU not present */
 #define CACHE_SIZE 4
 
+#elif CONFIG_CPU == IMX233
+#define USE_MMU
+#define CACHE_SIZE 16
+
 #else
 #error Cache settings unknown for this CPU !
 
-- 
cgit