From 05099149f193cac0c81b0129c17feb78b1a9681a Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sun, 6 Apr 2008 04:34:57 +0000 Subject: Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/i2c-pp.c | 2 +- firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c | 2 +- firmware/target/arm/ipod/app.lds | 56 +++++++++++++++++++---- firmware/target/arm/ipod/boot.lds | 2 + firmware/target/arm/iriver/app.lds | 56 +++++++++++++++++++---- firmware/target/arm/iriver/boot.lds | 2 + firmware/target/arm/iriver/h10/lcd-h10_20gb.c | 2 +- firmware/target/arm/olympus/app.lds | 56 +++++++++++++++++++---- firmware/target/arm/olympus/boot.lds | 2 + firmware/target/arm/pcm-pp.c | 6 +-- firmware/target/arm/sandisk/app.lds | 56 +++++++++++++++++++---- firmware/target/arm/sandisk/ata-c200_e200.c | 2 +- firmware/target/arm/sandisk/boot.lds | 2 + firmware/target/arm/sandisk/sansa-c200/lcd-c200.c | 2 +- firmware/target/arm/sandisk/sansa-e200/lcd-e200.c | 4 +- firmware/target/arm/system-target.h | 2 +- firmware/target/arm/tcc780x/ata-nand-tcc780x.c | 2 +- 17 files changed, 204 insertions(+), 52 deletions(-) (limited to 'firmware/target/arm') diff --git a/firmware/target/arm/i2c-pp.c b/firmware/target/arm/i2c-pp.c index 450effc32d..40eb80cfe1 100644 --- a/firmware/target/arm/i2c-pp.c +++ b/firmware/target/arm/i2c-pp.c @@ -33,7 +33,7 @@ #include "as3514.h" /* Local functions definitions */ -static struct mutex i2c_mtx NOCACHEBSS_ATTR; +static struct mutex i2c_mtx SHAREDBSS_ATTR; #define POLL_TIMEOUT (HZ) diff --git a/firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c b/firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c index f80412023d..564eb2e642 100644 --- a/firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c +++ b/firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c @@ -22,7 +22,7 @@ #include "hwcompat.h" #include "kernel.h" -static struct mutex adc_mtx NOCACHEBSS_ATTR; +static struct mutex adc_mtx SHAREDBSS_ATTR; /* used in the 2nd gen ADC interrupt */ static unsigned int_data; diff --git a/firmware/target/arm/ipod/app.lds b/firmware/target/arm/ipod/app.lds index 765a5f0389..54af494d72 100644 --- a/firmware/target/arm/ipod/app.lds +++ b/firmware/target/arm/ipod/app.lds @@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o) #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif + +#define CACHEALIGN_SIZE 16 + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +78,18 @@ SECTIONS _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +123,7 @@ SECTIONS _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +136,7 @@ SECTIONS cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +144,53 @@ SECTIONS stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - diff --git a/firmware/target/arm/ipod/boot.lds b/firmware/target/arm/ipod/boot.lds index 2f2f4f91a1..1f9c65d31c 100644 --- a/firmware/target/arm/ipod/boot.lds +++ b/firmware/target/arm/ipod/boot.lds @@ -43,6 +43,7 @@ SECTIONS *(.irodata) *(.idata) *(.data*) + *(.ncdata*); _dataend = . ; } @@ -64,6 +65,7 @@ SECTIONS _edata = .; *(.bss*); *(.ibss); + *(.ncbss*); _end = .; } } diff --git a/firmware/target/arm/iriver/app.lds b/firmware/target/arm/iriver/app.lds index 765a5f0389..54af494d72 100644 --- a/firmware/target/arm/iriver/app.lds +++ b/firmware/target/arm/iriver/app.lds @@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o) #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif + +#define CACHEALIGN_SIZE 16 + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +78,18 @@ SECTIONS _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +123,7 @@ SECTIONS _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +136,7 @@ SECTIONS cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +144,53 @@ SECTIONS stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - diff --git a/firmware/target/arm/iriver/boot.lds b/firmware/target/arm/iriver/boot.lds index 5fbe999333..971ec6627b 100644 --- a/firmware/target/arm/iriver/boot.lds +++ b/firmware/target/arm/iriver/boot.lds @@ -27,6 +27,7 @@ SECTIONS *(.irodata) *(.idata) *(.data*) + *(.ncdata*); _dataend = . ; } @@ -48,6 +49,7 @@ SECTIONS _edata = .; *(.bss*); *(.ibss); + *(.ncbss*); _end = .; } } diff --git a/firmware/target/arm/iriver/h10/lcd-h10_20gb.c b/firmware/target/arm/iriver/h10/lcd-h10_20gb.c index 1c4116d2e7..1ee43c390f 100644 --- a/firmware/target/arm/iriver/h10/lcd-h10_20gb.c +++ b/firmware/target/arm/iriver/h10/lcd-h10_20gb.c @@ -34,7 +34,7 @@ static unsigned short disp_control_rev; /* Contrast setting << 8 */ static int lcd_contrast; -static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0; +static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0; /* Forward declarations */ static void lcd_display_off(void); diff --git a/firmware/target/arm/olympus/app.lds b/firmware/target/arm/olympus/app.lds index 765a5f0389..54af494d72 100644 --- a/firmware/target/arm/olympus/app.lds +++ b/firmware/target/arm/olympus/app.lds @@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o) #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif + +#define CACHEALIGN_SIZE 16 + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +78,18 @@ SECTIONS _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +123,7 @@ SECTIONS _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +136,7 @@ SECTIONS cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +144,53 @@ SECTIONS stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - diff --git a/firmware/target/arm/olympus/boot.lds b/firmware/target/arm/olympus/boot.lds index 5fbe999333..2c0245072c 100644 --- a/firmware/target/arm/olympus/boot.lds +++ b/firmware/target/arm/olympus/boot.lds @@ -27,6 +27,7 @@ SECTIONS *(.irodata) *(.idata) *(.data*) + *(.ncdata*) _dataend = . ; } @@ -48,6 +49,7 @@ SECTIONS _edata = .; *(.bss*); *(.ibss); + *(.ncbss*); _end = .; } } diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c index 433e6e1e4f..64c6d0cdc8 100644 --- a/firmware/target/arm/pcm-pp.c +++ b/firmware/target/arm/pcm-pp.c @@ -72,7 +72,7 @@ void fiq_handler(void) /**************************************************************************** ** Playback DMA transfer **/ -struct dma_data dma_play_data NOCACHEBSS_ATTR = +struct dma_data dma_play_data SHAREDBSS_ATTR = { /* Initialize to a locked, stopped state */ .p = NULL, @@ -84,7 +84,7 @@ struct dma_data dma_play_data NOCACHEBSS_ATTR = .state = 0 }; -static unsigned long pcm_freq NOCACHEDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */ +static unsigned long pcm_freq SHAREDDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */ #ifdef HAVE_WM8751 /* Samplerate control for audio codec */ static int sr_ctrl = MROBE100_44100HZ; @@ -356,7 +356,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count) **/ #ifdef HAVE_RECORDING /* PCM recording interrupt routine lockout */ -static struct dma_data dma_rec_data NOCACHEBSS_ATTR = +static struct dma_data dma_rec_data SHAREDBSS_ATTR = { /* Initialize to a locked, stopped state */ .p = NULL, diff --git a/firmware/target/arm/sandisk/app.lds b/firmware/target/arm/sandisk/app.lds index 765a5f0389..54af494d72 100644 --- a/firmware/target/arm/sandisk/app.lds +++ b/firmware/target/arm/sandisk/app.lds @@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o) #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif + +#define CACHEALIGN_SIZE 16 + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +78,18 @@ SECTIONS _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +123,7 @@ SECTIONS _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +136,7 @@ SECTIONS cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +144,53 @@ SECTIONS stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - diff --git a/firmware/target/arm/sandisk/ata-c200_e200.c b/firmware/target/arm/sandisk/ata-c200_e200.c index 747cb17ca1..e4a5388978 100644 --- a/firmware/target/arm/sandisk/ata-c200_e200.c +++ b/firmware/target/arm/sandisk/ata-c200_e200.c @@ -165,7 +165,7 @@ static struct sd_card_status sd_status[NUM_VOLUMES] = /* Shoot for around 75% usage */ static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x1c0)/sizeof(long)]; static const char sd_thread_name[] = "ata/sd"; -static struct mutex sd_mtx NOCACHEBSS_ATTR; +static struct mutex sd_mtx SHAREDBSS_ATTR; static struct event_queue sd_queue; /* Posted when card plugged status has changed */ diff --git a/firmware/target/arm/sandisk/boot.lds b/firmware/target/arm/sandisk/boot.lds index a087a7250d..1c1066895f 100644 --- a/firmware/target/arm/sandisk/boot.lds +++ b/firmware/target/arm/sandisk/boot.lds @@ -30,6 +30,7 @@ SECTIONS *(.irodata) *(.idata) *(.data*) + *(.ncdata*) _dataend = . ; } @@ -51,6 +52,7 @@ SECTIONS _edata = .; *(.bss*); *(.ibss); + *(.ncbss*); _end = .; } } diff --git a/firmware/target/arm/sandisk/sansa-c200/lcd-c200.c b/firmware/target/arm/sandisk/sansa-c200/lcd-c200.c index a629739d50..a2110f7e66 100644 --- a/firmware/target/arm/sandisk/sansa-c200/lcd-c200.c +++ b/firmware/target/arm/sandisk/sansa-c200/lcd-c200.c @@ -23,7 +23,7 @@ #include "system.h" /* Display status */ -static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0; +static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0; /* LCD command set for Samsung S6B33B2 */ diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c index f2689eabbf..15263b5533 100644 --- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c @@ -28,8 +28,8 @@ /* Power and display status */ static bool power_on = false; /* Is the power turned on? */ -static bool display_on NOCACHEBSS_ATTR = false; /* Is the display turned on? */ -static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0; +static bool display_on SHAREDBSS_ATTR = false; /* Is the display turned on? */ +static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0; /* Reverse Flag */ #define R_DISP_CONTROL_NORMAL 0x0004 diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 8dcbf0f9da..2a72b524f7 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h @@ -108,7 +108,7 @@ static inline unsigned int processor_id(void) /* Certain data needs to be out of the way of cache line interference * such as data for COP use or for use with UNCACHED_ADDR */ #define PROC_NEEDS_CACHEALIGN -#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ +#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ /** cache functions **/ #ifndef BOOTLOADER diff --git a/firmware/target/arm/tcc780x/ata-nand-tcc780x.c b/firmware/target/arm/tcc780x/ata-nand-tcc780x.c index f6d1df96ce..b47444f3a8 100644 --- a/firmware/target/arm/tcc780x/ata-nand-tcc780x.c +++ b/firmware/target/arm/tcc780x/ata-nand-tcc780x.c @@ -42,7 +42,7 @@ static bool initialized = false; static long next_yield = 0; #define MIN_YIELD_PERIOD 2000 -static struct mutex ata_mtx NOCACHEBSS_ATTR; +static struct mutex ata_mtx SHAREDBSS_ATTR; #define SECTOR_SIZE 512 -- cgit