jz4760b Amaury Pouly mips (xburst) 1.0 IPU_P IPU_P
0x13080000
 CPM Clock, Reset and Power Module CPM
0xb0000000
 SYSCLK Clock control register SYSCLK
0x0
 EXCLK_DIV Only applies to APB periperals: UART, I2S, I2C, SSI, SADC, OTG, etc 31 BY_1 0x0 BY_2 0x1 MEM_TYPE 30 MDDR_SDRAM 0x0 DDR_DD2 0x1 SCLK_DIV 24 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 EN_CHANGE 22 PLL_DIV Only applies to MSC, I2S, LCD, UHC, OTG, SSI, PCM, GPU and GPS. 21 BY_2 0x0 BY_1 0x1 H2CLK_DIV 16 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 MCLK_DIV 12 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 PCLK_DIV 8 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 HCLK_DIV 4 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 CCLK_DIV 0 4 BY_1 0x0 BY_2 0x1 BY_3 0x2 BY_4 0x3 BY_6 0x4 BY_8 0x5 LOWPWR Low power control register LOWPWR
0x4
 AHB1_PWD 30 VBAT_IR 29 GPS_PWD 28 AHB1S_PWD 26 GPSS_PWD 24 PWR_STABILITY_TIME 8 12 DUTY 3 5 DOZE 2 SLEEP_MODE 0 2 IDLE 0x0 SLEEP 0x1 RESET Reset status register RESETSTS
0x8
 PWRUP_STS 2 WATCHDOG_STS 1 PWRON_STS 0 PLLCTRL0 PLL control register 0 PLLCTRL0
0x10
 FEED_DIV PLLM 24 7 IN_DIV PLLN 18 4 OUT_DIV PLLOD 16 2 BY_1 0x0 BY_2 0x1 BY_4 0x2 BY_8 0x3 LOCK LOCK0 bit 15 EN_LOCK 14 STABLE 10 BYPASS 9 ENABLE 8 STABILIZE_TIME 0 8 PLLSWITCH PLL switch and status register PLLSWITCH
0x14
 OFF_STS 31 BYPASS_STS 30 ON_STS 29 ENABLE_STS 28 FREQ_STS 27 SRC_STS 26 SYS_CHANGE_MODE 2 HW 0x0 STOP 0x1 SRC_SWITCH_MODE 1 SLOW 0x0 FAST 0x1 FREQ_CHANGE_MODE 0 SLOW 0x0 FAST 0x1 CLKGATE0 Clock gate register 0 CLKGATE0
0x20
 EMC 31 DDR 30 IPU 29 LCD 28 TVE 27 CIM 26 MDMA 25 UHC 24 MAC 23 GPS 22 DMAC 21 SSI2 20 SSI1 19 UART3 18 UART2 17 UART1 16 UART0 15 SADC 14 KBC 13 MSC2 12 MSC1 11 OWI 10 TSSI 9 AIC 8 SCC 7 I2C1 6 I2C0 5 SSI0 4 MSC0 3 OTG 2 BCH 1 NEMC 0 OSCPWR Oscillator and power control register OSCPWR
0x24
 STABILIZE_TIME 8 8 OTG_SUSPEND 7 GPS_ENABLE 6 UHC_SUSPEND SPENDH bit 5 OSC_SLEEP 4 P0_SLEEP 3 SRC_SEL 2 EXCLK_DIV_512 0x0 RTCLK 0x1 CLKGATE1 Clock gate register 1 CLKGATE1
0x28
 AUX 11 OSD 10 GPU 9 PCM 8 AHB1 7 CABAC 6 SRAM 5 DCT 4 ME 3 DBLK 2 MC 1 BDMA 0 PLLCTRL1 PLL control register 1 PLLCTRL1
0x30
 FEED_DIV 24 7 IN_DIV 18 4 OUT_DIV 16 2 BY_1 0x0 BY_2 0x1 BY_4 0x2 BY_8 0x3 SRC_SEL 15 EXCLK 0x0 PLL0 0x1 PLL0_DIV 9 6 ENABLE 7 STABLE 6 LOCK LOCK1 bit 2 OFF 1 ON 0 SCRATCH CPM scratch pad register SCRATCH
0x34
 SCRATCHPROT CPM scratch pad protected register SCRATCHPROT
0x38
 USBCTRL OTG parameter control register USBCTRL
0x3c
 USB_MODE 31 AVLD_REG 30 IDPULLUP IDPULLUP_MASK bit 28 2 INCRM INCR_MASK bit 27 CLK12_EN 26 COMMONONN 25 VBUSVLDEXT 24 VBUSVLDEXTSEL 23 POR 22 SIDDQ 21 OTG_DISABLE 20 COMPDISTUNE 17 3 OTGTUNE 14 3 SQRXTUNE 11 3 TXFSLSTUNE 7 4 TXPREEMPHTUNE 6 TXRISETUNE 4 2 TXVREFTUNE 0 4 USBRESET OTG reset detect timer register USBRESET
0x40
 VBFIL_LD_EN 25 IDDIG_EN 24 IDDIG_REG 23 USBRDT 0 23 USBVBUS USBVBUS
0x44
 USBCLK OTG PHY clock divider register USBCLK
0x50
 SRC_SEL 31 EXCLK 0x0 PLL 0x1 PLL_SEL 30 PLL0 0x0 PLL1 0x1 DIV 0 6 I2SCLK I2S device clock divider register I2SCLK
0x60
 SRC_SEL 31 EXCLK 0x0 PLL 0x1 PLL_SEL 30 PLL0 0x0 PLL1 0x1 DIV 0 9 LCDCLK LCD pix clock divider register LCDCLK
0x64
 OUT_SEL 30 LCD_PANEL 0x0 TV_ENC 0x1 PLL_SEL 29 PLL0 0x0 PLL1 0x1 DIV 0 11 MSCCLK MSC clock divider register MSCCLK
0x68
 SRC_SEL 31 EXCLK 0x0 PLL 0x1 DIV 0 6 UHCCLK UHC device clock divider register UHCCLK
0x6c
 PLL_SEL 31 PLL0 0x0 PLL1 0x1 DIV 0 4 SSICLK SSI clock divider register SSICLK
0x74
 SRC_SEL 31 EXCLK 0x0 PLL 0x1 DIV 0 6 CIMCLK CIM mclk clock divider register CIM
0x7c
 DIV 0 8 GPSCLK GPS clock divider register GPS
0x80
 PLL_SEL 31 PLL0 0x0 PLL1 0x1 DIV 0 4 PCMCLK PCM device clock divider register PCMCLK
0x84
 SRC_SEL 31 EXCLK 0x0 PLL 0x1 PLL_SEL 30 PLL0 0x0 PLL1 0x1 DIV PCMCDR bit 0 9 GPUCLK GPUCLK
0x88
 PLL_SEL 31 PLL0 0x0 PLL1 0x1 DIV 0 3 PSWC0ST PSWC0ST
0x90
 PSWC1ST PSWC1ST
0x94
 PSWC2ST PSWC2ST
0x98
 PSWC3ST PSWC3ST
0x9c
 INTC INTC (Interrupt Controller) INTC
0xb0001000
 STATUS STATUS 0 2 0x00 + (n) * 0x20 MASK MASK 0 2 0x04 + (n) * 0x20 set 4 clr 8 PENDING PENDING 0 2 0x10 + (n) * 0x20 OST Operating System Timer OST
0xb0002000
 DATA Data register DATA
0xe0
 COUNTL Count (low part) COUNTL
0xe4
 COUNTH Count (high-part) COUNTH
0xe8
 CTRL Operating system control register CTRL
0xec
 16 IGNORE_COMPARE 15 SHUTDOWN 9 GRACEFUL 0x0 ABRUPT 0x1 PRESCALE 3 3 1 0x0 4 0x1 16 0x2 64 0x3 256 0x4 1024 0x5 EXT_EN 2 RTC_EN 1 PCK_EN 0 COUNTH_BUF COUNTH_BUF
0xfc
 TCU Timer and counter unit module TCU
0xb0002000
 ENABLE Timer counter enable register ENABLE
0x10
 16 OST 15 TIMER 0 8 set 4 clr 8 STOP Timer stop register STOP
0x1c
 WDT 16 OST 15 TIMER 0 8 set 16 clr 32 FLAG Timer flag register FLAG
0x20
 HALF 16 8 OST 15 FULL 0 8 set 4 clr 8 MASK Timer mask register TMR
0x30
 HALF 16 8 OST 15 FULL 0 8 set 4 clr 8 DATA_FULL Timer data full register DATA_FULL 0 8 (n) * 0x10 + 0x40 16 COUNT 0 16 DATA_HALF Timer data half register DATA_HALF 0 8 (n) * 0x10 + 0x44 16 COUNT 0 16 COUNT Timer counter register COUNT 0 8 (n) * 0x10 + 0x48 16 COUNT 0 16 CTRL Timer control register CTRL 0 8 (n) * 0x10 + 0x4c 16 CLEAR_TO_ZERO 10 SHUTDOWN 9 GRACEFUL 0x0 ABRUPT 0x1 PMW_INIT_LVL 8 PWM_EN 7 PWM_IN_EN 6 PRESCALE 3 3 1 0x0 4 0x1 16 0x2 64 0x3 256 0x4 1024 0x5 EXT_EN 2 RTC_EN 1 PCK_EN 0 STATUS Timer status register TSTR
0xf0
 REAL2 18 REAL1 17 BUSY2 2 BUSY1 1 set 4 clr 8 WDT Watchdog timer module WDT
0xb0002000
 DATA DATA
0x0
 16 ENABLE Watchdog counter enable register ENABLE
0x4
 8 TCEN 0 COUNT COUNT
0x8
 16 CTRL Watchdog control register CTRL
0xc
 16 PRESCALE 3 3 1 0x0 4 0x1 16 0x2 64 0x3 256 0x4 1024 0x5 CLKIN 0 3 PCK 0x1 RTC 0x2 EXT 0x4 RTC Real time clock module(RTC) address definition RTC
0xb0003000
 RTCCR RTC control register RTCCR
0x0
 WRDY 7 1HZ 6 1HZIE 5 AF 4 AIE 3 AE 2 SELEXC 1 RTCE 0 RTCSR RTCSR
0x4
 RTCSAR RTCSAR
0x8
 RTCGR RTC regulator register RTCGR
0xc
 LOCK 31 ADJC 16 10 NC1HZ 0 16 HCR Hibernate control register HCR
0x20
 PD 0 HWFCR Hibernate wakeup filter counter register HWFCR
0x24
 HWFCR 5 11 HRCR Hibernate reset counter register HRCR
0x28
 HRCR 5 7 HWCR Hibernate wakeup control register HWCR
0x2c
 EPDET 3 WKUPVL 2 EALM 0 HWRSR Hibernate wakeup status register HWRSR
0x30
 APD 8 HR 5 PPR 4 PIN 1 ALM 0 HSPR Hibernate scratch pattern register HSPR
0x34
 WENR write enable pattern register WENR
0x3c
 WEN 31 WENPAT 0 16 GPIO General purpose I/O port module(GPIO) address definition GPIO
0xb0010000
 IN Port IN IN 0 6 (n)*0x100 + 0x00 OUT Port OUT OUT 0 6 (n)*0x100 + 0x10 set 4 clr 8 FLAG_CLEAR FLGC 0 6 (n)*0x100 + 0x14 MASK MASK 0 6 (n)*0x100 + 0x20 set 4 clr 8 PULL PULL 0 6 (n)*0x100 + 0x30 set 4 clr 8 FUNCTION Function FUNCTION 0 6 (n)*0x100 + 0x40 set 4 clr 8 SELECT Select SELECT 0 6 (n)*0x100 + 0x50 set 4 clr 8 DIR Direction DIR 0 6 (n)*0x100 + 0x60 set 4 clr 8 TRIGGER Trigger TRIGGER 0 6 (n)*0x100 + 0x70 set 4 clr 8 FLAG Flag FLG 0 6 (n)*0x100 + 0x80 DRIVE0 Drive strength 0 DRIVE0 0 6 (n)*0x100 + 0xc0 set 4 clr 8 DRIVE1 DRIVE1 0 6 (n)*0x100 + 0xd0 set 4 clr 8 DRIVE2 DRIVE2 0 6 (n)*0x100 + 0xe0 set 4 clr 8 SLEW Slew rate control SLEW 0 6 (n)*0x100 + 0xf0 set 4 clr 8 AIC AC97 and I2S controller module AIC
0xb0020000
 FR AIC controller configuration register FR
0x0
 RFTH 24 4 TFTH 16 5 LSMP 6 ICDC 5 AUSEL 4 RST 3 BCKD 2 SYNCD 1 ENB 0 CR AIC controller common control register CR
0x4
 PACK16 28 CHANNEL 24 3 OSS 19 3 ISS 16 3 RDMS 15 TDMS 14 M2S 11 ENDSW 10 AVSTSU 9 TFLUSH 8 RFLUSH 7 EROR 6 ETUR 5 ERFS 4 ETFS 3 ENLBF 2 ERPL 1 EREC 0 ACCR1 AIC controller AC-link control register 1 ACCR1
0x8
 RS 16 10 XS 0 10 ACCR2 AIC controller AC-link control register 2 ACCR2
0xc
 ERSTO 18 ESADR 17 ECADT 16 SO 3 SR 2 SS 1 SA 0 I2SCR AIC controller i2s/msb-justified control register I2SCR
0x10
 RFIRST 17 SWLH 16 STPBK 12 ESCLK 4 AMSL 0 SR AIC controller FIFO status register SR
0x14
 RFL 24 6 TFL 8 6 ROR 6 TUR 5 RFS 4 TFS 3 ACSR AIC controller AC-link status register ACSR
0x18
 SLTERR 21 CRDY 20 CLPM 19 RSTO 18 SADR 17 CADT 16 I2SSR AIC controller I2S/MSB-justified status register I2SSR
0x1c
 CHBSY 5 TBSY 4 RBSY 3 BSY 2 ACCAR AIC controller AC97 codec command address register ACCAR
0x20
 CAR 0 20 ACCDR AIC controller AC97 codec command data register ACCDR
0x24
 CDR 0 20 ACSAR AIC controller AC97 codec status address register ACSAR
0x28
 SAR 0 20 ACSDR AIC controller AC97 codec status data register ACSDR
0x2c
 SDR 0 20 I2SDIV AIC controller I2S/MSB-justified clock divider register I2SDIV
0x30
 DIV 0 4 DR DR
0x34
 SPENA SPDIF enable register SPENA
0x80
 SPEN 0 SPCTRL SPDIF control register SPCTRL
0x84
 DMAEN 15 DTYPE 14 SIGN 13 INVALID 12 RST 11 SPDIFI2S 10 MTRIG 1 MFFUR 0 SPSTATE SPDIF state register SPSTATE
0x88
 FLVL 8 7 BUSY 7 FTRIG 1 FUR 0 SPCFG1 SPDIF configure 1 register SPCFG1
0x8c
 INITLVL 17 ZROVLD 16 TRIG 12 2 SRCNUM 8 4 CH1NUM 4 4 CH2NUM 0 4 SPCFG2 SPDIF configure 2 register SPCFG2
0x90
 FS 26 4 ORGFRQ 22 4 SAMWL 19 3 MAXWL 18 CLKACU 16 2 CATCODE 8 8 CHMD 6 2 PRE 3 COPYN 2 AUDION 1 CONPRO 0 SPFIFO SPFIFO
0x94
 RGADW ICDC internal register access control register RGADW
0xa4
 RGWR 16 RGADDR 8 7 RGDIN 0 8 RGDATA ICDC internal register data output register RGDATA
0xa8
 IRQ 8 RGDOUT 0 8 MSC MSC 0
0xb0021000
0xb0022000
0xb0023000
 STRPCL MSC Clock and Control Register STRPCL
0x0
 16 SEND_CCSD send command completion signal disable to ceata 15 SEND_AS_CCSD send internally generated stop after sending ccsd 14 EXIT_MULTIPLE 7 EXIT_TRANSFER 6 START_READWAIT 5 STOP_READWAIT 4 RESET 3 START_OP 2 CLOCK_CONTROL Start MMC/SD clock 0 2 STOP 0x1 START 0x2 STAT MSC Status Register STAT
0x4
 AUTO_CMD_DONE 12 is internally generated by controller has finished 31 IS_RESETTING 15 SDIO_INT_ACTIVE 14 PRG_DONE 13 DATA_TRAN_DONE 12 END_CMD_RES 11 DATA_FIFO_AFULL 10 IS_READWAIT 9 CLK_EN 8 DATA_FIFO_FULL 7 DATA_FIFO_EMPTY 6 CRC_RES_ERR 5 CRC_READ_ERROR 4 CRC_WRITE_ERROR No CRC status is sent back 2 2 NO 0x0 DATA 0x1 NOSTS 0x2 TIME_OUT_RES 1 TIME_OUT_READ 0 CLKRT MSC Bus Clock Control Register CLKRT
0x8
 16 CLK_RATE 1/128 of CLK_SRC 0 3 DIV_1 0x0 DIV_2 0x1 DIV_4 0x2 DIV_8 0x3 DIV_16 0x4 DIV_32 0x5 DIV_64 0x6 DIV_128 0x7 CMDAT MSC Command Sequence Control Register CMDAT
0xc
 CCS_EXPECTED interrupts are enabled in ce-ata 31 READ_CEATA 30 SDIO_PRDT exact 2 cycle 17 SEND_AS_STOP 16 RTRG reset value 14 2 EQUALT_8 0x0 EQUALT_16 0x1 EQUALT_24 0x2 TTRG reset value 12 2 LESS_8 0x0 LESS_16 0x1 LESS_24 0x2 STOP_ABORT 11 BUS_WIDTH 8-bit data bus 9 2 1BIT 0x0 4BIT 0x2 8BIT 0x3 DMA_EN 8 INIT 7 BUSY 6 STREAM_BLOCK 5 WRITE 4 DATA_EN 3 RESPONSE Format R6 0 3 NONE 0x0 R1 0x1 R2 0x2 R3 0x3 R4 0x4 R5 0x5 R6 0x6 RESTO RESTO
0x10
 16 RDTO RDTO
0x14
 BLKLEN BLKLEN
0x18
 16 NOB NOB
0x1c
 16 SNOB SNOB
0x20
 16 IMASK MSC Interrupts Mask Register IMASK
0x24
 AUTO_CMD_DONE 15 DATA_FIFO_FULL 14 DATA_FIFO_EMP 13 CRC_RES_ERR 12 CRC_READ_ERR 11 CRC_WRITE_ERR 10 TIMEOUT_RES 9 TIMEOUT_READ 8 SDIO 7 TXFIFO_WR_REQ 6 RXFIFO_RD_REQ 5 END_CMD_RES 2 PRG_DONE 1 DATA_TRAN_DONE 0 IREG MSC Interrupts Status Register IREG
0x28
 16 AUTO_CMD_DONE 15 DATA_FIFO_FULL 14 DATA_FIFO_EMP 13 CRC_RES_ERR 12 CRC_READ_ERR 11 CRC_WRITE_ERR 10 TIMEOUT_RES 9 TIMEOUT_READ 8 SDIO 7 TXFIFO_WR_REQ 6 RXFIFO_RD_REQ 5 END_CMD_RES 2 PRG_DONE 1 DATA_TRAN_DONE 0 CMD CMD
0x2c
 8 ARG ARG
0x30
 RES RES
0x34
 16 RXFIFO RXFIFO
0x38
 TXFIFO TXFIFO
0x3c
 LPM MSC Low Power Mode Register LPM
0x40
 LPM 0 UART UART 0
0xb0030000
0xb0031000
0xb0032000
0xb0033000
 DLLR DLLR
0x0
 RDR RDR
0x0
 TDR TDR
0x0
 DLHR DLHR
0x4
 IER IER
0x4
 RTIE 0: receive timeout interrupt disable 4 MIE 0: modem status interrupt disable 3 RLIE 0: receive line status interrupt disable 2 TIE 0: transmit fifo empty interrupt disable 1 RIE 0: receive fifo full interrupt disable 0 FCR FCR
0x8
 RTRG_4 6 UUE 0: disable UART 4 DMS 0: disable DMA mode 3 TFLS write 1 to flush transmit FIFO 2 RFLS write 1 to flush receive FIFO 1 FE 0: non-FIFO mode 1: FIFO mode 0 ISR ISR
0x8
 IID_THRI Transmitter holding register empty 1 IP 0: interrupt is pending 1: no interrupt 0 LCR LCR
0xc
 DLAB 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR 7 SBRK write 0 normal, write 1 send break 6 SPAR 0: sticky parity disable 5 PROE 0: even parity 1: odd parity 4 PE 0: parity disable 3 STOP2 2 WLEN_6 0 MCR MCR
0x10
 MCE 0: modem function is disable 7 FCM 0: software 1: hardware 6 LOOP 0: normal 1: loopback mode 4 RTS 0: RTS_ output high, 1: RTS_ output low 1 LSR LSR
0x14
 RFER 0: no receive error 1: receive error in FIFO mode 7 TEMT 1: transmit FIFO and shift registers empty 6 TDRQ 1: transmit FIFO half 'empty' 5 BRK 0: no break detected 1: receive a break signal 4 FER 0; no framing error 3 PER 0: no parity error 2 ORER 0: no overrun error 1 DR 0: receive FIFO is empty 1: receive data is ready 0 MSR MSR
0x18
 SPR SPR
0x1c
 SIRCR SIRCR
0x20
 RDPL 0: decoder interprets positive pulse as 0 4 TDPL 0: encoder generates a positive pulse for 0 3 TPWS 0: transmit 0 pulse width is 3/16 of bit length, 1: 0 pulse width is 1.6us for 115.2Kbps 2 RSIRE 0: receiver is in UART mode 1: SIR mode 1 TSIRE 0: transmitter is in UART mode 1: SIR mode 0 UMR UMR
0x24
 UACR UACR
0x28
 SCC SCC
0xb0040000
 DR DR
0x0
 8 FDR SCC FIFO Data Count Register FDR
0x4
 8 CR SCC Control Register CR
0x8
 SCCE 31 TRS 30 T2R 29 FDIV SCC_CLK frequency is half of device clock 24 2 1 0x0 2 0x1 FLUSH 23 TRIG Receive/Transmit-FIFO Trigger is 14 16 2 1 0x0 4 0x1 8 0x2 14 0x3 TP 15 CONV 14 TXIE 13 RXIE 12 TENDIE 11 RTOIE 10 ECIE 9 EPIE 8 RETIE 7 EOIE 6 TSEND 3 PX SCC_CLK stops at state high 1 2 NOT_SUPPORT 0x0 STOP_LOW 0x1 STOP_HIGH 0x2 CLKSTP 0 SR SCC Status Register SR
0xc
 16 TRANS 15 ORER 12 RTO 11 PER 10 TFTG 9 RFTG 8 TEND 7 RETR_3 4 ECNTO 0 TFR TFR
0x10
 16 EGTR EGTR
0x14
 8 ECR ECR
0x18
 RTOR RTOR
0x1c
 8 SSI SSI (Synchronous Serial Interface) SSI 0
0xb0043000
0xb0044000
0xb0045000
 DR SSI Data Register DR
0x0
 GPC 0 9 CR0 SSI Control Register 0 CR0
0x4
 16 SSIE 15 TIE 14 RIE 13 TEIE 12 REIE 11 LOOP 10 RFINE 9 RFINC 8 EACLRUN hardware auto clear underrun when TxFifo no empty 7 FSEL 6 TFLUSH 2 RFLUSH 1 DISREV 0 CR1 SSI Control Register 1 CR1
0x8
 FRMHL SSI_CE_ is high valid and SSI_CE2_ is high valid 30 2 CELOW_CE2LOW 0x0 CEHIGH_CE2LOW 0x1 CELOW_CE2HIGH 0x2 CEHIGH_CE2HIGH 0x3 TFVCK 28 2 0 0x0 1 0x1 2 0x2 3 0x3 TCKFI 26 2 0 0x0 1 0x1 2 0x2 3 0x3 LFST 25 ITFRM 24 UNFIN 23 MULTS 22 FMAT National Microwire 2 format 20 2 SPI 0x0 SSP 0x1 MW1 0x2 MW2 0x3 TTRG SSI1 TX trigger 16 4 MCOM 16-bit command selected 12 4 1BIT 0x0 2BIT 0x1 3BIT 0x2 4BIT 0x3 5BIT 0x4 6BIT 0x5 7BIT 0x6 8BIT 0x7 9BIT 0x8 10BIT 0x9 11BIT 0xa 12BIT 0xb 13BIT 0xc 14BIT 0xd 15BIT 0xe 16BIT 0xf RTRG SSI RX trigger 8 4 FLEN 4 4 2BIT 0x0 3BIT 0x1 4BIT 0x2 5BIT 0x3 6BIT 0x4 7BIT 0x5 8BIT 0x6 9BIT 0x7 10BIT 0x8 11BIT 0x9 12BIT 0xa 13BIT 0xb 14BIT 0xc 15BIT 0xd 16BIT 0xe 17BIT 0xf PHA 1 POL 0 SR SSI Status Register SR
0xc
 TFIFONUM 16 8 RFIFONUM 8 8 END 7 BUSY 6 TFF 5 RFE 4 TFHE 3 RFHF 2 UNDR 1 OVER 0 ITR SSI Interval Time Control Register ITR
0x10
 16 CNTCLK 15 IVLTM 0 15 ICR ICR
0x14
 8 GR GR
0x18
 16 I2C I2C I2C 0
0xb0050000
0xb0051000
0xb0055000
 CTRL I2C Control Register CTRL
0x0
 8 STPHLD 7 SLVDIS after reset slave is disabled 6 REST 5 MATP 1: 10bit address 0: 7bit addressing 4 SATP standard mode 100kbps 3 SPD standard mode 100kbps 1 2 SPDS 0x1 SPDF 0x2 MD master enabled 0 TAR I2C target address TAR
0x4
 16 MATP 12 SPECIAL 11 GC_OR_START 10 SAR SAR
0x8
 16 DC I2C data buffer and command DC
0x10
 16 CMD 1 read 0 write 8 SHCNT I2C standard mode high count register SHCNT
0x14
 16 SLCNT I2C standard mode low count register SLCNT
0x18
 16 FHCNT I2C fast mode high count register FHCNT
0x1c
 16 FLCNT I2C fast mode low count register FLCNT
0x20
 16 INTST i2c interrupt status INTST
0x2c
 16 IGC 11 ISTT 10 ISTP 9 IACT 8 RXDN 7 TXABT 6 RDREQ 5 TXEMP 4 TXOF 3 RXFL 2 RXOF 1 RXUF 0 INTM i2c interrupt mask status INTM
0x30
 16 MIGC 11 MISTT 10 MISTP 9 MIACT 8 MRXDN 7 MTXABT 6 MRDREQ 5 MTXEMP 4 MTXOF 3 MRXFL 2 MRXOF 1 MRXUF 0 RXTL RXTL
0x38
 8 TXTL TXTL
0x3c
 8 CINTR I2C Clear Combined and Individual Interrupts CINTR
0x40
 8 CRXUF CRXUF
0x44
 8 CRXOF CRXOF
0x48
 8 CTXOF CTXOF
0x4c
 8 CRXREQ CRXREQ
0x50
 8 CTXABRT CTXABRT
0x54
 8 CRXDONE CRXDONE
0x58
 8 CACT CACT
0x5c
 8 CSTP CSTP
0x60
 8 CSTT CSTT
0x64
 16 CGC CGC
0x68
 8 ENB I2C Enable ENB
0x6c
 8 I2CENB Enable the i2c 0 STA I2C Status Register STA
0x70
 8 SLVACT Slave FSM is not in IDLE state 6 MSTACT Master FSM is not in IDLE state 5 RFF RFIFO if full 4 RFNE RFIFO is not empty 3 TFE TFIFO is empty 2 TFNF TFIFO is not full 1 ACT I2C Activity Status 0 TXFLR TXFLR
0x74
 8 RXFLR RXFLR
0x78
 8 TXABRT I2C Transmit Abort Status Register TXABRT
0x80
 16 SLVRD_INTX 15 SLV_ARBLOST 14 SLVFLUSH_TXFIFO 13 ARB_LOST 12 ABRT_MASTER_DIS 11 ABRT_10B_RD_NORSTRT 10 SBYTE_NORSTRT 9 ABRT_HS_NORSTRT 8 SBYTE_ACKDET 7 ABRT_HS_ACKD 6 ABRT_GCALL_READ 5 ABRT_GCALL_NOACK 4 ABRT_XDATA_NOACK 3 ABRT_10ADDR2_NOACK 2 ABRT_10ADDR1_NOACK 1 ABRT_7B_ADDR_NOACK 0 DMACR DMACR
0x88
 8 DMATDLR DMATDLR
0x8c
 8 DMARDLR DMARDLR
0x90
 8 SDASU SDASU
0x94
 8 ACKGC ACKGC
0x98
 8 ENSTA I2C Enable Status Register ENSTA
0x9c
 8 SLVRDLST 2 SLVDISB 1 I2CEN when read as 1, i2c is deemed to be in an enabled state, when read as 0, i2c is deemed completely inactive. The cpu can, safely read this bit anytime .When this bit is read as 0 ,the cpu can, safely read SLVRDLST and SLVDISB 0 SDAHD SDAHD
0xd0
 16 HOLD_TIME_EN 8 PS2 APB BUS Devices Base PS2
0xb0060000
 SADC SAR A/D Controller SADC
0xb0070000
 ENABLE ADC Enable Register ENABLE
0x0
 8 POWER 7 SLEEP 6 TOUCH_EN 2 VBAT_EN 1 AUX_EN 0 CFG ADC Configure Register CFG
0x4
 SP_ZZ 31 DMA_EN 15 XYZ 13 2 XYS 0x0 XYD 0x1 XYZ1Z2 0x2 SAMPLE_COUNT 10 3 CMD 0 2 AUX 0x0 AUX1 0x1 AUX2_VBAT 0x2 CTRL ADC Control Register CTRL
0x8
 8 SLEEP_PEN_DOWN_MASK 5 PEN_DOWN_MASK 4 PEN_UP_MASK 3 TOUCH_MASK 2 VBAT_MASK 1 AUX_MASK 0 STATUS ADC Status Register STATUS
0xc
 8 SLEEP_RDY 7 SLEEP_PEN_DOWN 5 PEN_DOWN 4 PEN_UP 3 TOUCH 2 VBAT 1 AUX 0 SAMEPOINT ADC Same Point Time Register SAME_POINT
0x10
 16 DELAY_US 0 16 PENWAIT ADC Wait Pen Down Time Register PEN_WAIT
0x14
 16 DELAY_MS 0 16 TOUCH ADC Touch Screen Data Register TOUCH
0x18
 TYPE1 31 DATA1 16 12 TYPE0 15 DATA0 0 12 VBAT ADC VBAT Date Register VBAT
0x1c
 16 DATA 0 12 AUX ADC AUX Data Register ADADAT
0x20
 16 DATA 0 12 FILTER ADC Filter Register FILTER
0x24
 16 ENABLE 15 DATA 0 12 CLK ADC Clock Divide Register CLK
0x28
 MS_DIV 16 16 US_DIV 8 8 ADC_DIV 0 8 PCM Pulse-code modulation module(PCM) address definition PCM 0
0xb0071000
0xb0074000
 PCTL PCM controller control register PCTL
0x0
 ERDMA 9 ETDMA 8 LSMP 7 ERPL 6 EREC 5 FLUSH 4 RST 3 CLKEN 1 PCMEN 0 PCFG PCM controller configure register PCFG
0x4
 SLOT 13 2 ISS_16BIT 12 OSS_16BIT 11 IMSBPOS 10 OMSBPOS 9 RFTH 5 4 TFTH 1 4 MODE_SLAVE 0 PDP PDP
0x8
 PINTC PCM controller interrupt control register PINTC
0xc
 ETFS 3 ETUR 2 ERFS 1 EROR 0 PINTS PCM controller interrupt status register PINTS
0x10
 RSTS 14 TFL 9 5 TFS 8 TUR 7 RFL 2 5 RFS 1 ROR 0 PDIV PCM controller clock division register PDIV
0x14
 SYNL 11 6 SYNDIV 6 5 CLKDIV 0 6 OWI OWI
0xb0072000
 OWICFG OWI configure register OWICFG
0x0
 8 MODE 7 RDDATA 6 WRDATA 5 RDST 4 WR1RD 3 WR0 2 RST 1 ENA 0 OWICTL OWI control register OWICTL
0x4
 8 EBYTE 2 EBIT 1 ERST 0 OWISTS OWI status register OWISTS
0x8
 8 PST 7 BYTE_RDY 2 BIT_RDY 1 PST_RDY 0 OWIDAT OWIDAT
0xc
 8 OWIDIV OWI clock divide register OWIDIV
0x10
 8 CLKDIV 0 6 TSSI TSSI MPEG 2-TS slave interface TSSI
0xb0073000
 ENA TSSI enable register ENA
0x0
 8 SFT_RST soft reset bit 7 FAIL fail signal bit 4 PEN_0 PID filter enable bit for PID 3 PID_EN soft filtering function enable bit 2 DMA_EN DMA enable bit 1 ENA TSSI enable bit 0 CFG TSSI configure register CFG
0x4
 16 TRIG fifo trig number 14 2 4 0x0 8 0x1 16 0x2 32 0x3 TRANS_MD 10 2 0 0x0 1 0x1 2 0x2 END_WD order of data in word 9 END_BT order of data in byte 8 TSDI_H data pin polarity 7 USE_0 serial mode data pin select: 0 for TSDI7, 1 for TSDI0 6 TSCLK_CH clk channel select 5 PARAL mode select 4 TSCLK_P clk edge select 3 TSFRM_H TSFRM polarity select 2 TSSTR_H TSSTR polarity select 1 TSFAIL_H TSFAIL polarity select 0 CTRL TSSI control register CTRL
0x8
 8 DTRM FIFO data trigger interrupt mask bit 2 OVRNM FIFO overrun interrupt mask bit 1 TRIGM FIFO trigger interrupt mask bit 0 STAT TSSI state register STAT
0xc
 8 DTR FIFO data trigger interrupt flag bit 2 OVRN FIFO overrun interrupt flag bit 1 TRIG FIFO trigger interrupt flag bit 0 FIFO TSSI FIFO register FIFO
0x10
 PEN TSSI PID enable register PEN
0x14
 EN151 31 EN141 30 EN131 29 EN121 28 EN111 27 EN101 26 EN91 25 EN81 24 EN71 23 EN61 22 EN51 21 EN41 20 EN31 19 EN21 18 EN11 17 EN01 16 EN150 15 EN140 14 EN130 13 EN120 12 EN110 11 EN100 10 EN90 9 EN80 8 EN70 7 EN60 6 EN50 5 EN40 4 EN30 3 EN20 2 EN10 1 EN00 enable PID n 0 NUM NUM
0x18
 DTR DTR
0x1c
 PID TSSI PID filter register PID 0 16 0x20 + 4*(n) PID1 16 13 PID0 0 13 DDA DDA
0x60
 DTA DTA
0x64
 DID DID
0x68
 DCMD DCMD
0x6c
 TLEN 8 8 TEFE 4 TSZ 2 2 4 0x0 8 0x1 16 0x2 32 0x3 TEIE 1 LINK 0 DST DST
0x70
 DID 16 16 TEND 0 TC TC
0x74
 OP 4 2 OPE 2 EME 1 APM 0 HARB0 AHB0 BUS Devices Base HARB0
0xb3000000
 EMC EMC (External Memory Controller) EMC
0xb3010000
 BCR Bus Control Register BCR
0x0
 BT_SEL 30 2 PK_SEL 24 BSR Nand and SDRAM Bus Share Select: 0, share; 1, unshare 2 SHARE 0x0 UNSHARE 0x1 BRE 1 ENDIAN 0 SMCR Static Memory Control Register SMCR 0 7 0x10 + (n)*4 STRV 24 4 TAW 20 4 TBP 16 4 TAH 12 3 TAS 8 3 BW 6 2 8BIT 0x0 16BIT 0x1 32BIT 0x2 BCM 3 BL 1 2 4 0x0 8 0x1 16 0x2 32 0x3 SMT 0 SACR Static Memory Bank Addr Config Reg SACR 0 5 0x30 + (n)*4 BASE 8 8 MASK 0 8 NFCSR NAND Flash Control/Status Register NFCSR
0x50
 NFCE4 NAND Flash Enable 7 NFE4 NAND Flash FCE# Assertion Enable 6 NFCE3 5 NFE3 4 NFCE2 3 NFE2 2 NFCE1 1 NFE1 0 DMCR DRAM Control Register DMCR
0x80
 BW 31 CA 26 3 8 0x0 9 0x1 10 0x2 11 0x3 12 0x4 RMODE 25 RFSH 24 MRSET 23 RA 20 2 11 0x0 12 0x1 13 0x2 BA 19 PDM 18 EPIN 17 MBSEL 16 TRAS 13 3 RCD 11 2 TPC 8 3 TRWL 5 2 TRC 2 3 TCL 0 2 RTCSR Refresh Time Control/Status Register RTCSR
0x84
 16 SFR self refresh flag 8 CMF 7 CKS 0 3 DISABLE 0x0 4 0x1 16 0x2 64 0x3 256 0x4 1024 0x5 2048 0x6 4096 0x7 RTCNT Refresh Timer Counter RTCNT
0x88
 16 RTCOR Refresh Time Constant Register RTCOR
0x8c
 16 DMAR SDRAM Bank Address Configuration Register DMAR 0 2 0x90 + (n)*4 BASE 8 8 MASK 0 8 PMEMBS1 PMEMBS1
0x6004
 PMEMBS0 PMEMBS0
0x6008
 SDMR Mode Register of SDRAM bank SDMR
0xa000
 BM Write Burst Mode 9 OM Operating Mode 7 2 NORMAL 0x0 CAS CAS Latency 4 3 1 0x1 2 0x2 3 0x3 BT Interleave 3 SEQ 0x0 INT 0x1 BL Burst Length 0 3 1 0x0 2 0x1 4 0x2 8 0x3 OTP OTP (One Time Programmable Module) [not sure about the address] OTP
0xb3012000
 ID0 ID0 Register ID0
0x0
 WID Wafer ID 24 8 MID MASK ID 16 8 FID Foundary ID 8 8 PID Product ID 0 8 ID1 ID1 Register ID1
0x4
 LID Lot ID 8 24 TID Test House ID 0 8 ID2 ID2 Register ID2
0x8
 XADR Die X-dir Address 24 8 YADR Die Y-dir Address 16 8 TDATE Testing Date 0 16 ID3 ID3 Register ID3
0xc
 CID Customer ID 16 16 CP Chip Parameters 0 16 BR0 BOOTROM0 Register BR0
0x10
 BR1 BOOTROM1 Register BR1
0x14
 UDCBOOT 27MHz OSC 0 8 27M 0x0 26M 0x3 13M 0xc 24M 0xf AUTO 0xf0 HW0 Chip Hardware 0 Register HW0
0x18
 HW1 Chip Hardware 1 Register HW1
0x1c
 DDRC DDRC
0xb3020000
 STATUS DDR Status Register STATUS
0x0
 ENDIAN 0 Little data endian, 1 Big data endian 7 MISS 6 DPDN 0 DDR memory is NOT in deep-power-down state, 1 DDR memory is in deep-power-down state 5 PDN 0 DDR memory is NOT in power-down state, 1 DDR memory is in power-down state 4 AREF 0 DDR memory is NOT in auto-refresh state, 1 DDR memory is in auto-refresh state 3 SREF 0 DDR memory is NOT in self-refresh state, 1 DDR memory is in self-refresh state 2 CKE1 0 CKE1 Pin is low, 1 CKE1 Pin is high 1 CKE0 0 CKE0 Pin is low, 1 CKE0 Pin is high 0 CFG DDR Configure Register CFG
0x4
 ROW1 Row Address width. 27 2 12 0x0 13 0x1 14 0x2 COL1 Row Address width. 25 2 8 0x0 9 0x1 10 0x2 11 0x3 BA1_BIT bank width 24 4 0x0 8 0x1 IMBA 23 BTRUN 21 MPRT Miss CS protect: 0 will lock the bus on fault, 1 will return random data 15 TYPE 12 3 DDR1 0x2 MDDR 0x3 DDR2 0x4 ROW0 Row Address width. 10 2 12 0x0 13 0x1 14 0x2 COL0 Row Address width. 8 2 8 0x0 9 0x1 10 0x2 11 0x3 CS1EN 0 DDR Pin CS1 un-used, 1 There're DDR memory connected to CS1 7 CS0EN 0 DDR Pin CS0 un-used, 1 There're DDR memory connected to CS0 6 CL CAS latency 2 4 3 0x0 4 0x1 5 0x2 6 0x3 BA0 bank width 1 4 0x0 8 0x1 DW External memory data width 0 16 0x0 32 0x1 CTRL DDR Control Register CTRL
0x8
 ACTPD 0 Precharge all banks before entering power-down, 1 Do not precharge banks before entering power-down 15 PDT Enter power-down after 128 tCK idle 12 3 DIS 0x0 8 0x1 16 0x2 32 0x3 64 0x4 128 0x5 PRET Precharge active bank after 128 tCK idle 8 3 DIS 0x0 8 0x1 16 0x2 32 0x3 64 0x4 128 0x5 SR 1 Drive external DDR device entering self-refresh mode, 0 Drive external DDR device exiting self-refresh mode 5 UNALIGN 0 Disable unaligned transfer on AXI BUS, 1 Enable unaligned transfer on AXI BUS 4 ALH Advanced Latency Hiding: 0 Disable ALH, 1 Enable ALH 3 RDC 0 dclk clock frequency is lower than 60MHz, 1 dclk clock frequency is higher than 60MHz 2 CKE 0 Not set CKE Pin High, 1 Set CKE Pin HIGH 1 RESET 0 End resetting ddrc_controller, 1 Resetting ddrc_controller 0 LMR DDR Load-Mode-Register LMR
0xc
 DDR_ADDR 16 8 BA (For mobile DDR) Status Register set 8 3 MRS 0x0 M_MRS 0x0 EMRS1 0x1 M_SR 0x1 EMRS2 0x2 M_EMRS 0x2 EMRS3 0x3 CMD Load Mode Register 4 2 PREC Precharge one/all bank 0x0 AUREF Auto-refresh 0x1 LMR Load-Mode reister 0x2 START 0 No command is performed, 1 On the posedge of START, perform a command defined by CMD field 0 TIMING1 DDR Timing Config Register 1 TIMING1
0x10
 TRAS ACTIVE to PRECHARGE command period (2 * tRAS + 1) 28 4 TRTP READ to PRECHARGE command period. 24 2 TRP PRECHARGE command period. 20 3 TRCD ACTIVE to READ or WRITE command period. 16 3 TRC ACTIVE to ACTIVE command period. 12 4 TRRD ACTIVE bank A to ACTIVE bank B command period. 8 2 DISABLE 0x0 2 0x1 3 0x2 4 0x3 TWR WRITE Recovery Time defined by register MR of DDR2 memory 4 3 1 0x0 2 0x1 3 0x2 4 0x3 5 0x4 6 0x5 TWTR WRITE to READ command delay. 0 2 1 0x0 2 0x1 3 0x2 4 0x3 TIMING2 DDR Timing Config Register 2 TIMING2
0x14
 TRFC AUTO-REFRESH command period. 24 4 RWCOV Equal to Tsel of MDELAY. 19 5 TMINSR Minimum Self-Refresh / Deep-Power-Down time 8 4 TXP EXIT-POWER-DOWN to next valid command period. 4 3 TMRD Load-Mode-Register to next valid command period. 0 2 REFCNT DDR Auto-Refresh Counter REFCNT
0x18
 CON Constant value used to compare with CNT value. 16 8 CNT 8-bit counter 8 8 CLKDIV Clock Divider for auto-refresh counter. 1 3 REF_EN Enable Refresh Counter 0 DQS DDR DQS Delay Control Register DQS
0x1c
 ERROR ahb_clk Delay Detect ERROR, read-only. 29 READY ahb_clk Delay Detect READY, read-only. 28 SRDET Hardware auto-redetect & set delay line 25 DET Start delay detecting. 24 AUTO Hardware auto-detect & set delay line 23 CLKD CLKD is reference value for setting WDQS and RDQS. 16 7 WDQS Set delay element number to write DQS delay-line. 8 6 RDQS Set delay element number to read DQS delay-line. 0 6 DQSADJ DDR DQS Delay Adjust Register DQSADJ
0x20
 WSIGN The sign of WDQS value for WRITE DQS delay 13 WDQS The adjust value for WRITE DQS delay 8 5 RSIGN The sign of RDQS value for READ DQS delay 5 RDQS The adjust value for READ DQS delay 0 5 MMAP DDR Memory Map Config Register MMAP 0 2 0x24 + 4*(n) BASE 8 8 MASK 0 8 DELAYCTRL DELAYCTRL
0x2c
 TSEL Ready delay select: adds betweee 0 and 3tCK 18 2 MSEL Mask delay select: adds betweee 0 and 3tCK 16 2 HL Half-clock delay: 1 adds 1/2tCK 15 QUAR Quarter clock delay select: 1 adds 1/4tCK 14 MAUTO 6 MSIGN Mask sign 5 MASK_DELAY_SEL_ADJ 0 5 DELAYCTRL2 DELAYCTRL2
0x30
 MASK_DELAY_SEL 0 5 PADCTRL0 Pad control 0 PADCTRL0
0x50
 PDDQS 28 4 PDDQ 24 4 SCHMITT_TRIGGER_DQS 20 4 SCHMITT_TRIGGER_DQ 16 4 ENPULL_DQS 12 4 ENPULL_DQ 8 4 PULLUP_DQS 4 4 PULLUP_DQ 0 4 PADCTRL1 Pad Control 1 PADCTRL1
0x54
 INEDQS 28 4 INEDQ 24 4 SSTL_MODE 16 STRENGTH_DQS 8 8 HALF_DDR1 0x0 HALF_MDDR 0x0 HALF_SDRAM_12MA 0x0 HALF_DDR2 0x55 HALF_SDRAM_16MA 0x55 FULL_DDR1 0xaa FULL_SDRAM_24MA 0xaa FULL_DDR2 0xff FULL_MDDR 0xff FULL_SDRAM_30MA 0xff STRENGTH_DQ 0 8 HALF_DDR1 0x0 HALF_MDDR 0x0 HALF_SDRAM_12MA 0x0 HALF_DDR2 0x55 HALF_SDRAM_16MA 0x55 FULL_DDR1 0xaa FULL_SDRAM_24MA 0xaa FULL_DDR2 0xff FULL_MDDR 0xff FULL_SDRAM_30MA 0xff PADCTRL2 Pad Control 2 PADCTRL2
0x58
 STRENGTH_CKO 18 2 STRENGTH_CKE 16 STRENGTH_ADDR 14 STRENGTH_DM3 12 STRENGTH_DM2 10 STRENGTH_DM1 8 STRENGTH_DM0 6 STRENGTH_CMD 4 STRENGTH_CS1 2 STRENGTH_CS0 0 PADCTRL3 Pad Control 3 PADCTRL3
0x5c
 MDMAC Memory Copy DMAC MDMAC
0xb3030000
 CH_SOURCE DMA source address CH_SOURCE 0 2 (0x00 + (n) * 0x20) CH_TARGET DMA target address CH_TARGET 0 2 (0x04 + (n) * 0x20) CH_COUNT DMA transfer count CH_COUNT 0 2 (0x08 + (n) * 0x20) CH_REQUEST DMA request source CH_REQUEST 0 2 (0x0c + (n) * 0x20) CH_CTRL DMA control/status CH_CTRL 0 2 (0x10 + (n) * 0x20) CH_CMD DMA command CH_CMD 0 2 (0x14 + (n) * 0x20) CH_DESC DMA descriptor address CH_DESC 0 2 (0x18 + (n) * 0x20) CH_STRIDE DMA Stride Address CH_STRIDE 0 2 (0xc0 + (n) * 0x04) CTRL DMA control register DMACR
0x300
 IRQ DMA interrupt pending IRQ
0x304
 DOORBELL DMA doorbell DOORBELL
0x308
 set 4 CLOCK CLOCK
0x310
 set 4 clr 0 EPD EPD EPD
0xb3050000
 CTRL CTRL
0x200
 PPL7_FRM_INTM 31 PPL6_FRM_INTM 30 PPL5_FRM_INTM 29 PPL4_FRM_INTM 28 PPL3_FRM_INTM 27 PPL2_FRM_INTM 26 PPL1_FRM_INTM 25 PPL0_FRM_INTM 24 FRM_VCOM_INTM 22 IMG_DONE_INTM 21 FRM_DONE_INTM 20 FRM_ABT_INTM 19 PWR_OFF_INTM 18 PWR_ON_INTM 17 DMA_DONE_INTM 16 PPL7_FRM_ENA 15 PPL6_FRM_ENA 14 PPL5_FRM_ENA 13 PPL4_FRM_ENA 12 PPL3_FRM_ENA 11 PPL2_FRM_ENA 10 PPL1_FRM_ENA 9 PPL0_FRM_ENA 8 IMG_REF_ABT 7 IMG_REF_ENA 6 PWROFF 5 PWRON 4 EPD_DMA_MODE 1 EPD_ENA 0 STA STA
0x204
 ISR ISR
0x208
 PPL7_FRM_INT 15 PPL6_FRM_INT 14 PPL5_FRM_INT 13 PPL4_FRM_INT 12 PPL3_FRM_INT 11 PPL2_FRM_INT 10 PPL1_FRM_INT 9 PPL0_FRM_INT 8 FRM_VCOM_INT 6 IMG_DONE_INT 5 FRM_DONE_INT 4 FRM_ABT_INT 3 PWR_OFF_INT 2 PWR_ON_INT 1 DMA_DONE_INT 0 CFG0 CFG0
0x20c
 DUAL_GATE 31 COLOR_MODE 30 COLOR_FORMAT 27 3 SDSP_CAS 26 SDSP_MODE 25 GDCLK_MODE 24 GDOE_MODE 22 2 GDUD 21 SDRL 20 GDCLK_POL 19 GDOE_POL 18 GDSP_POL 17 SDCLK_POL 16 SDOE_POL 15 SDSP_POL 14 SDCE_POL 13 SDLE_POL 12 GDSP_CAS 9 COMP_MODE 8 EPD_OBPP 1 3 EPD_OMODE 0 CFG1 CFG1
0x210
 SDDO_REV 30 PDAT_SWAP 29 SDCE_REV 28 SDOS 16 8 PADDING_DAT 8 8 SDCE_STN 4 4 SDCE_NUM 0 4 PPL0 PPL0
0x214
 PPL3_FRM_NUM 24 8 PPL2_FRM_NUM 16 8 PPL1_FRM_NUM 8 8 PPL0_FRM_NUM 0 8 PPL1 PPL1
0x218
 PPL7_FRM_NUM 24 8 PPL6_FRM_NUM 16 8 PPL5_FRM_NUM 8 8 PPL4_FRM_NUM 0 8 VAT VAT
0x21c
 VT 16 12 HT 0 12 DAV DAV
0x220
 VDE 16 12 VDS 0 12 DAH DAH
0x224
 HDE 16 12 HDS 0 12 VSYNC VSYNC
0x228
 VPE 16 12 VPS 0 12 HSYNC HSYNC
0x22c
 HPE 16 12 HPS 0 12 GDCLK GDCLK
0x230
 DIS 16 12 ENA 0 12 GDOE GDOE
0x234
 DIS 16 12 ENA 0 12 GDSP GDSP
0x238
 DIS 16 12 ENA 0 12 SDOE SDOE
0x23c
 DIS 16 12 ENA 0 12 SDSP SDSP
0x240
 DIS 16 12 ENA 0 12 PMGR0 PMGR0
0x244
 PWR_DLY12 16 12 PWR_DLY01 0 12 PMGR1 PMGR1
0x248
 PWR_DLY34 16 12 PWR_DLY23 0 12 PMGR2 PMGR2
0x24c
 PWR_DLY56 16 12 PWR_DLY45 0 12 PMGR3 PMGR3
0x250
 VCOM_IDLE 30 2 PWRCOM_POL 29 UNI_POL 28 PPL7_BDR_ENA 27 BDR_LEVEL 26 BDR_VALUE 24 2 PWR_POL 16 8 PWR_DLY67 0 12 PMGR4 PMGR4
0x254
 PWR_VAL 16 8 PWR_ENA 0 8 VCOM0 VCOM0
0x258
 VCOM1 VCOM1
0x25c
 VCOM2 VCOM2
0x260
 VCOM3 VCOM3
0x264
 VCOM4 VCOM4
0x268
 VCOM5 VCOM5
0x26c
 BORDR BORDR
0x270
 PPL_POS PPL_POS 0
0x280
0x288
0x290
0x298
0x2a0
0x2a8
0x2b0
0x2b8
 PPL_YPOS 16 12 PPL_XPOS 0 12 PPL_SIZE PPL_SIZE 1
0x28c
0x294
0x29c
0x2a4
0x2ac
0x2b4
0x2bc
 PPL_HEIGHT 16 12 PPL_WIDTH 0 12 LCD LCD (LCD Controller) LCD
0xb3050000
 CFG LCD Configure Register CFG
0x0
 LCDPIN LCD pins selection 31 LCD 0x0 SLCD 0x1 TVEPEH TVE PAL enable extra halfline signal 30 FUHOLD hold pixel clock when outFIFO underrun 29 NEWDES use new descripter. old: 4words, new:8words 28 PALBP bypass data format and alpha blending 27 TVEN indicate the terminal is lcd or tv 26 RECOVER Auto recover when output fifo underrun 25 DITHER Dither function 24 PSM PS signal mode 23 CLSM CLS signal mode 22 SPLM SPL signal mode 21 REVM REV signal mode 20 HSYNM HSYNC signal mode 19 PCLKM PCLK signal mode 18 INVDAT Inverse output data 17 SYNDIR_IN VSYNC&HSYNC direction 16 PSP PS pin reset state 15 CLSP CLS pin reset state 14 SPLP SPL pin reset state 13 REVP REV pin reset state 12 HSP HSYNC polarity:0-active high,1-active low 11 PCP PCLK polarity:0-rising,1-falling 10 DEP DE polarity:0-active high,1-active low 9 VSP VSYNC polarity:0-rising,1-falling 8 MODE_TFT_18BIT 18bit TFT 7 MODE_TFT_24BIT 24bit TFT 6 PDW LCD_D[0:7]/LCD_D[8:15] 4 2 1 0x0 2 0x1 4 0x2 8 0x3 MODE 16,18 bit TFT 0 4 GENERIC_TFT 0x0 SPECIAL_TFT_1 0x1 SPECIAL_TFT_2 0x2 SPECIAL_TFT_3 0x3 NONINTER_CCIR656 0x4 INTER_CCIR656 0x6 SINGLE_CSTN 0x8 SINGLE_MSTN 0x9 DUAL_CSTN 0xa DUAL_MSTN 0xb SERIAL_TFT 0xc LCM 0xd VSYNC Vertical Synchronize Register VSYNC
0x4
 VPS VSYNC pulse start in line clock, fixed to 0 16 16 VPE VSYNC pulse end in line clock 0 16 HSYNC Horizontal Synchronize Register HSYNC
0x8
 HPS HSYNC pulse start position in dot clock 16 16 HPE HSYNC pulse end position in dot clock 0 16 VAT Virtual Area Setting Register VAT
0xc
 HT Horizontal Total size in dot clock 16 16 VT Vertical Total size in dot clock 0 16 DAH Display Area Horizontal Start/End Point DAH
0x10
 HDS Horizontal display area start in dot clock 16 16 HDE Horizontal display area end in dot clock 0 16 DAV Display Area Vertical Start/End Point DAV
0x14
 VDS Vertical display area start in line clock 16 16 VDE Vertical display area end in line clock 0 16 PS PS Signal Setting PS
0x18
 PSS PS signal start position in dot clock 16 16 PSE PS signal end position in dot clock 0 16 CLS CLS Signal Setting CLS
0x1c
 CLSS CLS signal start position in dot clock 16 16 CLSE CLS signal end position in dot clock 0 16 SPL SPL Signal Setting SPL
0x20
 SPLS SPL signal start position in dot clock 16 16 SPLE SPL signal end position in dot clock 0 16 REV REV Signal Setting REV
0x24
 REVS REV signal start position in dot clock 16 16 CTRL LCD Control Register CTRL
0x30
 PINMD This register set Pin distribution in 16-bit parallel mode, 0: 16-bit data correspond with LCD_D[15:0], 1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] 31 BST 16-word contiue 28 3 4 0x0 8 0x1 16 0x2 32 0x3 64 0x4 16_CTN 0x5 C16 0x5 RGB555 RGB555 mode(foreground 0 in OSD mode) 27 OFUP Output FIFO underrun protection enable 26 FRC 2 grayscale 24 2 16 0x0 4 0x1 2 0x2 PDD Load Palette Delay Counter 16 8 EOFM EOF interrupt mask 13 SOFM SOF interrupt mask 12 OFUM Output FIFO underrun interrupt mask 11 IFUM0 Input FIFO 0 underrun interrupt mask 10 IFUM1 Input FIFO 1 underrun interrupt mask 9 LDDM LCD disable done interrupt mask 8 QDM LCD quick disable done interrupt mask 7 BEDN Endian selection 6 PEDN Endian in byte:0-msb first, 1-lsb first 5 DIS Disable indicate bit 4 ENA LCD enable bit 3 BPP 30 bpp 0 3 1 0x0 2 0x1 4 0x2 8 0x3 16 0x4 18_24 0x5 CMPS_24 0x6 30 0x7 STATE LCD Status Register STATE
0x34
 FEND 22 PWRUP 20 PWRDN 19 QD Quick Disable Done 7 EOF EOF Flag 5 SOF SOF Flag 4 OFU Output FIFO Underrun 3 IFU0 Input FIFO 0 Underrun 2 IFU1 Input FIFO 1 Underrun 1 LDD LCD Disabled 0 IID Interrupt ID Register IID
0x38
 DA Descriptor Address Register 1 DA 0
0x40
0x50
 SA Source Address Register 1 SA 0
0x44
0x54
 FID Frame ID Register 1 FID 0
0x48
0x58
 CMD DMA Command Register 1 CMD 0
0x4c
0x5c
 SOFINT 31 EOFINT 30 CMD indicate command in slcd mode 29 PAL 28 LEN 0 24 OFFS DMA Offsize Register 1 OFFS 0
0x60
0x70
 PW DMA Page Width Register 1 PW 0
0x64
0x74
 CNUM DMA Command Counter Register 1 CNUM 0
0x68
0x78
 DESSIZE Foreground Size in Descriptor 1 Register DESSIZE 0
0x6c
0x7c
 HEIGHT height of foreground 1 16 16 WIDTH width of foreground 1 0 16 RGBC RGB Controll Register RGBC
0x90
 16 RGBDM enable RGB Dummy data 15 DMM RGB Dummy mode 14 YCC RGB to YCC 8 ODDRGB odd line serial RGB data arrangement 4 3 EVENRGB even line serial RGB data arrangement 0 3 OSDC LCD OSD Configure Register OSDC
0x100
 16 SOFM1 Start of frame interrupt mask for foreground 1 15 EOFM1 End of frame interrupt mask for foreground 1 14 SOFM0 Start of frame interrupt mask for foreground 0 11 EOFM0 End of frame interrupt mask for foreground 0 10 ENDM End of frame interrupt mask for panel. 9 F1EN enable foreground 1 4 F0EN enable foreground 0 3 ALPHAEN enable alpha blending 2 ALPHAMD alpha blending mode 1 OSDEN OSD mode enable 0 OSDCTRL LCD OSD Control Register OSDCTRL
0x104
 16 IPU input data from IPU 15 RGB555 foreground 1, 16bpp, 0-RGB565, 1-RGB555 4 CHANGES Change size flag 3 OSDBPP RGB 30 bit 0 3 2 0x1 4 0x2 15_16 0x4 16 0x4 18_24 0x5 CMPS_24 0x6 30 0x7 OSDS LCD OSD Status Register OSDS
0x108
 16 SOF1 Start of frame flag for foreground 1 15 EOF1 End of frame flag for foreground 1 14 SOF0 Start of frame flag for foreground 0 11 EOF0 End of frame flag for foreground 0 10 READY Read for accept the change 0 BGC LCD Background Color Register BGC
0x10c
 RED Red color offset 16 8 GREEN Green color offset 8 8 BLUE Blue color offset 0 8 KEY LCD Foreground Color Key Register 1 KEY 0
0x110
0x114
 KEYEN enable color key 31 KEYMD color key mode 30 RED Red color offset 16 8 GREEN Green color offset 8 8 BLUE Blue color offset 0 8 ALPHA LCD ALPHA Register ALPHA
0x118
 8 IPUR LCD IPU Restart Register IPUR
0x11c
 IPUREN IPU restart function enable 31 XYP Foreground 1 XY Position Register XYP 0
0x120
0x124
 YPOS Y position bit of foreground 0 or 1 16 16 XPOS X position bit of foreground 0 or 1 0 16 SIZE Foreground 1 Size Register SIZE 0
0x128
0x12c
 DA0_PART2 Descriptor Address Register PART2 DA0_PART2
0x1c0
 SA0_PART2 Source Address Register PART2 SA0_PART2
0x1c4
 FID0_PART2 Frame ID Register PART2 FID0_PART2
0x1c8
 CMD0_PART2 DMA Command Register PART2 CMD0_PART2
0x1cc
 OFFS0_PART2 DMA Offsize Register PART2 OFFS0_PART2
0x1e0
 PW0_PART2 DMA Command Counter Register PART2 PW0_PART2
0x1e4
 CNUM0_PART2 Foreground Size in Descriptor PART2 Register CNUM0_PART2
0x1e8
 DESSIZE0_PART2 DESSIZE0_PART2
0x1ec
 XYP0_PART2 Foreground 0 PART2 XY Position Register XYP0_PART2
0x1f0
 SIZE0_PART2 Foreground 0 PART2 Size Register SIZE0_PART2
0x1f4
 PCFG PCFG
0x2c0
 SLCD Smart LCD Controller SLCD
0xb3050000
 MCFG SLCD Configure Register SCFG
0xa0
 DATA_WIDTH 10 3 18BIT 0x0 16BIT 0x1 8BIT_x3 0x2 8BIT_x2 0x3 8BIT_x1 0x4 24BIT 0x5 9BIT_x2 0x7 CMD_WIDTH 8 2 16BIT 0x0 8BIT 0x1 18BIT 0x2 24BIT 0x3 CS_ACTIVE_HIGH 4 RS_CMD_HIGH 3 CLK_ACTIVE_RISING 1 TYPE_SERIAL 0 MCTRL SLCD Control Register SCTRL
0xa4
 8 DMA_MODE 2 DMA_START 1 DMA_EN 0 MSTATE SLCD Status Register SSTATE
0xa8
 8 BUSY 0 MDATA SLCD Data Register MDATA
0xac
 RS_COMMAND 31 TVE TVE (TV Encoder Controller) TVE
0xb3050100
 CTRL TV Encoder Control register CTRL
0x40
 EYCBCR YCbCr_enable 25 ECVBS 1: cvbs_enable 0: s-video 24 DAPD3 DAC 3 power down 23 DAPD2 DAC 2 power down 22 DAPD1 DAC 1 power down 21 DAPD power down all DACs 20 YCDLY 16 3 CGAIN gain = 3/4 14 2 FULL 0x0 QUTR 0x1 HALF 0x2 THREE_QURT 0x3 CBW Ultra wide band 12 2 NARROW 0x0 WIDE 0x1 EXTRA 0x2 ULTRA 0x3 SYNCT 9 PAL 1: PAL, 0: NTSC 8 FINV invert_top:1-invert top and bottom fields. 7 ZBLACK bypass_yclamp:1-Black of luminance (Y) input is 0. 6 CR1ST uv_order:0-Cb before Cr,1-Cr before Cb 5 CLBAR Color bar mode:0-Output input video to TV,1-Output color bar to TV 4 SWRST Software reset:1-TVE is reset 0 FRCFG Frame configure register FRCFG
0x44
 L1ST 16 8 NLINE 0 10 SLCFG1 TV signal level configure register 1 SLCFG1
0x50
 WHITEL 16 10 BLACKL 0 10 SLCFG2 TV signal level configure register 2 SLCFG2
0x54
 VBLANKL 16 10 BLANKL 0 10 SLCFG3 TV signal level configure register 3 SLCFG3
0x58
 SYNCL 0 8 LTCFG1 Line timing configure register 1 LTCFG1
0x60
 FRONTP 16 5 HSYNCW 8 7 BACKP 0 7 LTCFG2 Line timing configure register 2 LTCFG2
0x64
 ACTLIN 16 11 PREBW 8 5 BURSTW 0 6 CFREQ Chrominance sub-carrier frequency configure register CFREQ
0x70
 CPHASE Chrominance sub-carrier phase configure register CPHASE
0x74
 INITPH 24 8 ACTPH 16 8 CCRSTP Never 0 2 8 0x0 4 0x1 2 0x2 0 0x3 CBCRCFG Chrominance filter configure register CBCRCFG
0x78
 CBBA 24 8 CRBA 16 8 CBGAIN 8 8 CRGAIN 0 8 WSSCR Wide screen signal control register WSSCR
0x80
 NCHFREQ 12 3 WSSEDGE 4 3 WSSCFG1 Wide screen signal configure register 1 WSSCFG1
0x84
 WSSCFG2 Wide screen signal configure register 2 WSSCFG2
0x88
 WSSCFG3 Wide screen signal configure register 3 WSSCFG3
0x8c
 CIM CIM
0xb3060000
 CFG CFG
0x0
 RXF_TRIG 24 6 SEP 20 ORDER CrY0CbY1; CrCbY 18 2 0 0x0 1 0x1 2 0x2 3 0x3 DF ITU656 YCbCr422 16 2 YUV444 0x1 YUV422 0x2 ITU656 0x3 INV_DAT 15 VSP VSYNC Polarity:0-rising edge active,1-falling edge active 14 HSP HSYNC Polarity:0-rising edge active,1-falling edge active 13 PCP PCLK working edge: 0-rising, 1-falling 12 DMA Suggested High speed AHB 10 2 BURST_INCR4 0x0 BURST_INCR8 0x1 BURST_INCR16 0x2 BURST_INCR32 0x3 DUMMY_ZERO 9 EXT_VSYNC Only for ITU656 Progressive mode 8 PACK 11 44 33 22 0xY0CrY1Cb 4 3 0 0x0 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 BYPASS 2 DSM Gated Clock Mode 0 2 CPM 0x0 CIM 0x1 GCM 0x2 CTRL CIM Control Register CTRL
0x4
 EEOF_LINE 20 12 FRC Sample 1/16 frame 16 4 1 0x0 2 0x1 3 0x2 4 0x3 5 0x4 6 0x5 7 0x6 8 0x7 9 0x8 10 0x9 11 0xa 12 0xb 13 0xc 14 0xd 15 0xe 16 0xf DMA_EEOFM Enable EEOF interrupt 15 WIN_EN 14 VDDM VDD interrupt enable 13 DMA_SOFM 12 DMA_EOFM 11 DMA_STOPM 10 RXF_TRIGM 9 RXF_OFM 8 DMA_SYNC when change DA, do frame sync 7 RXF_TRIG trigger value = (n+1)*burst_type 3 4 DMA_EN Enable DMA 2 RXF_RST RxFIFO reset 1 ENA Enable CIM 0 STATE CIM State Register STATE
0x8
 CR_RF_OF 27 CR_RF_TRIG 26 CR_RF_EMPTY 25 CB_RF_OF 19 CB_RF_TRIG 18 CB_RF_EMPTY 17 Y_RF_OF 11 Y_RF_TRIG 10 Y_RF_EMPTY 9 DMA_EEOF DMA Line EEOf irq 7 DMA_SOF DMA start irq 6 DMA_EOF DMA end irq 5 DMA_STOP DMA stop irq 4 RXF_OF RXFIFO over flow irq 3 RXF_TRIG RXFIFO triger meet irq 2 RXF_EMPTY RXFIFO empty irq 1 VDD CIM disabled irq 0 IID IID
0xc
 RXFIFO RXFIFO
0x10
 DA DA
0x20
 FA FA
0x24
 FID FID
0x28
 CMD CIM DMA Command Register CMD
0x2c
 SOFINT enable DMA start irq 31 EOFINT enable DMA end irq 30 EEOFINT enable DMA EEOF irq 29 STOP enable DMA stop irq 28 OFRCV enable recovery when TXFiFo overflow 27 LEN 0 24 SIZE CIM Window-Image Size Register SIZE
0x30
 LPF Lines per freame for csc output image 16 13 PPL Pixels per line for csc output image, should be an even number 0 13 OFFSET CIM Image Offset Register OFFSET
0x34
 V Vertical offset 16 12 H OFFSET_H should be even number 0 12 YFA YFA
0x38
 YCMD YCMD
0x3c
 CBFA CBFA
0x40
 CBCMD CBCMD
0x44
 CRFA CRFA
0x48
 CRCMD CRCMD
0x4c
 CTRL2 CTRL2
0x50
 OPG 4 2 OPE 2 EME 1 APM 0 RAM_ADDR RAM_ADDR
0x1000
 IPU IPU
0xb3080000
 IPU_V IPU_V
0xb3080000
 HARB1 AHB1 BUS Devices Base HARB1
0xb3200000
 DMAGP0 DMAGP0
0xb3210000
 DMAGP1 DMAGP1
0xb3220000
 DMAGP2 DMAGP2
0xb3230000
 MC MC
0xb3250000
 MCCR MC Control Register MCCR
0x0
 MCSR MC Status Register MCSR
0x4
 MCRBAR MCRBAR
0x8
 MCT1LFCR MCT1LFCR
0xc
 MCT2LFCR MCT2LFCR
0x10
 MCCBAR MCCBAR
0x14
 MCIIR MCIIR
0x18
 MCSIR MCSIR
0x1c
 MCT1MFCR MCT1MFCR
0x20
 MCT2MFCR MCT2MFCR
0x24
 MCFGIR MCFGIR
0x28
 MCFCIR MCFCIR
0x2c
 MCRNDTR MCRNDTR
0x40
 MC2CR MC2CR
0x8000
 MC2SR MC2SR
0x8004
 MC2RBAR MC2RBAR
0x8008
 MC2CBAR MC2CBAR
0x800c
 MC2IIR MC2IIR
0x8010
 MC2TFCR MC2TFCR
0x8014
 MC2SIR MC2SIR
0x8018
 MC2FCIR MC2FCIR
0x801c
 MC2RNDTR MC2RNDTR
0x8040
 ME ME
0xb3260000
 MECR ME control register MECR
0x0
 MERBAR MERBAR
0x4
 MECBAR MECBAR
0x8
 MEDAR MEDAR
0xc
 MERFSR MERFSR
0x10
 MECFSR MECFSR
0x14
 MEDFSR MEDFSR
0x18
 MESR ME settings register MESR
0x1c
 MEMR ME MVD register MEMR
0x20
 MEFR ME flag register MEFR
0x24
 DEBLK DEBLK
0xb3270000
 IDCT IDCT
0xb3280000
 CABAC CABAC
0xb3290000
 HARB2 AHB2 BUS Devices Base HARB2
0xb3400000
 NEMC NEMC
0xb3410000
 SMC SMC 1
0x14
0x18
0x1c
0x20
0x24
0x28
 STRV 24 5 TAW 20 4 TBP 16 4 TAH 12 4 TAS 8 4 BW 6 2 8BIT 0x0 16BIT 0x1 BL 1 2 4 0x0 8 0x1 16 0x2 32 0x3 SMT 0 SMA SMA 1
0x34
0x38
0x3c
0x40
0x44
0x48
 BASE 8 8 MASK 0 8 NFC NAND Flash Control/Status Register NFC
0x50
 NFCE4 NAND Flash Enable 7 NFE4 NAND Flash FCE# Assertion Enable 6 NFCE3 5 NFE3 4 NFCE2 3 NFE2 2 NFCE1 1 NFE1 0 PNC PNC
0x100
 PND PND
0x104
 BITCNT BITCNT
0x108
 DMAC DMAC (DMA Controller) DMAC
0xb3420000
 DSAR DMA source address DSAR 0 12 ((n)/6*0x100 + 0x00 + ((n)-(n)/6*6) * 0x20) DTAR DMA target address DTAR 0 12 ((n)/6*0x100 + 0x04 + ((n)-(n)/6*6) * 0x20) DTCR DMA transfer count DTCR 0 12 ((n)/6*0x100 + 0x08 + ((n)-(n)/6*6) * 0x20) DRSR DMA request source DRSR 0 12 ((n)/6*0x100 + 0x0c + ((n)-(n)/6*6) * 0x20) RS 0 6 AUTO 0x8 TSSIIN 0x9 EXTERN 0xc UART3OUT 0xe UART3IN 0xf UART2OUT 0x10 UART2IN 0x11 UART1OUT 0x12 UART1IN 0x13 UART0OUT 0x14 UART0IN 0x15 SSI0OUT 0x16 SSI0IN 0x17 AICOUT 0x18 AICIN 0x19 MSC0OUT 0x1a MSC0IN 0x1b TCU 0x1c SADC 0x1d MSC1OUT 0x1e MSC1IN 0x1f SSI1OUT 0x20 SSI1IN 0x21 PMOUT 0x22 PMIN 0x23 MSC2OUT 0x24 MSC2IN 0x25 DCCSR DMA control/status DCCSR 0 12 ((n)/6*0x100 + 0x10 + ((n)-(n)/6*6) * 0x20) NDES descriptor (0) or not (1) ? 31 DES8 Descriptor 8 Word 30 CDOA copy of DMA offset address 16 8 AR address error 4 TT transfer terminated 3 HLT DMA halted 2 CT count terminated 1 EN channel enable bit 0 DCMD DMA command DCMD 0 12 ((n)/6*0x100 + 0x14 + ((n)-(n)/6*6) * 0x20) EACKS_LOW External DACK Output Level Select, active low 31 EACKM_WRITE External DACK Output Mode Select, output in write cycle 30 ERDM External DREQ Detection Mode Select 28 2 LOW 0x0 FALL 0x1 HIGH 0x2 RISE 0x3 SAI source address increment 23 DAI dest address increment 22 RDIL request detection interval length 16 4 IGN 0x0 2 0x1 4 0x2 8 0x3 12 0x4 16 0x5 20 0x6 24 0x7 28 0x8 32 0x9 48 0xa 60 0xb 64 0xc 124 0xd 128 0xe 200 0xf SWDH source port width 14 2 32 0x0 8 0x1 16 0x2 DWDH dest port width 12 2 32 0x0 8 0x1 16 0x2 DS transfer data size of a data unit 8 3 32BIT 0x0 8BIT 0x1 16BIT 0x2 16BYTE 0x3 32BYTE 0x4 64BYTE 0x5 STDE Stride Disable/Enable 2 TIE DMA transfer interrupt enable 1 LINK descriptor link enable 0 DDA DMA descriptor address DDA 0 12 ((n)/6*0x100 + 0x18 + ((n)-(n)/6*6) * 0x20) BASE descriptor base address 12 20 OFFSET descriptor offset address 4 8 DSD DMA Stride Address DSD 0 12 ((n)/6*0x100 + 0x1c + ((n)-(n)/6*6) * 0x04) TSD target stride address 16 16 SSD source stride address 0 16 DMACR DMA control register DMACR 0 2 0x0300 + 0x100 * (m) FMSC MSC Fast DMA mode 31 FSSI SSI Fast DMA mode 30 FTSSI TSSI Fast DMA mode 29 FUART UART Fast DMA mode 28 FAIC AIC Fast DMA mode 27 PR channel priority mode 8 2 012345 0x0 120345 0x1 230145 0x2 340125 0x3 HLT DMA halt flag 3 AR address error flag 2 DMAE DMA enable bit 0 DMAIPR DMA interrupt pending DMAIPR 0 2 0x0304 + 0x100 * (m) CIRQ5 irq pending status for channel 5 5 CIRQ4 irq pending status for channel 4 4 CIRQ3 irq pending status for channel 3 3 CIRQ2 irq pending status for channel 2 2 CIRQ1 irq pending status for channel 1 1 CIRQ0 irq pending status for channel 0 0 DMADBR DMA doorbell DMADBR 0 2 0x0308 + 0x100 * (m) DB5 doorbell for channel 5 5 DB4 doorbell for channel 4 4 DB3 doorbell for channel 3 3 DB2 doorbell for channel 2 2 DB1 doorbell for channel 1 1 DB0 doorbell for channel 0 0 DMADBSR DMA doorbell set DMADBSR 0 2 0x030C + 0x100 * (m) DBS5 enable doorbell for channel 5 5 DBS4 enable doorbell for channel 4 4 DBS3 enable doorbell for channel 3 3 DBS2 enable doorbell for channel 2 2 DBS1 enable doorbell for channel 1 1 DBS0 enable doorbell for channel 0 0 DMACK DMACK 0 2 0x0310 + 0x100 * (m) DMACKS DMACKS 0 2 0x0314 + 0x100 * (m) DMACKC DMACKC 0 2 0x0318 + 0x100 * (m) UHC UHC
0xb3430000
 USB USB
0xb3440000
 FADDR Function Address 8-bit FADDR
0x0
 POWER Power register bit masks POWER
0x1
 SOFTCONN 6 HSENAB 5 HSMODE 4 RESUME 2 SUSPENDM 0 INTRIN Interrupt IN 16-bit INTRIN
0x2
 INTROUT Interrupt OUT 16-bit INTROUT
0x4
 INTRINE Intr IN enable 16-bit INTRINE
0x6
 INTROUTE Intr OUT enable 16-bit INTROUTE
0x8
 INTRUSB Interrupt register bit masks INTRUSB
0xa
 RESET 2 RESUME 1 SUSPEND 0 INTRUSBE Interrupt USB Enable 8-bit INTRUSBE
0xb
 FRAME Frame number 16-bit FRAME
0xc
 INDEX Index register 8-bit INDEX
0xe
 TESTMODE Testmode register bits TESTMODE
0xf
 PACKET 3 K 2 J 1 SE0NAK 0 INMAXP EP1-2 IN Max Pkt Size 16-bit INMAXP
0x10
 CSR0 CSR0 bit masks CSR0
0x12
 SVDSETUPEND 7 SVDOUTPKTRDY 6 SENDSTALL 5 SETUPEND 4 DATAEND 3 SENTSTALL 2 INPKTRDY 1 OUTPKTRDY 0 INCSR EP1-2 IN CSR LSB 8/16bit INCSR
0x12
 CDT 6 SENTSTALL 5 SENDSTALL 4 FF 3 UNDERRUN 2 FFNOTEMPT 1 INPKTRDY 0 INCSRH Endpoint CSR register bits INCSRH
0x13
 AUTOSET 7 ISO 6 MODE 5 DMAREQENAB 4 DMAREQMODE 2 OUTMAXP EP1 OUT Max Pkt Size 16-bit OUTMAXP
0x14
 OUTCSR EP1 OUT CSR LSB 8/16bit OUTCSR
0x16
 CDT 7 SENTSTALL 6 SENDSTALL 5 FF 4 DATAERR 3 OVERRUN 2 FFFULL 1 OUTPKTRDY 0 OUTCSRH EP1 OUT CSR MSB 8-bit OUTCSRH
0x17
 AUTOCLR 7 ISO 6 DMAREQENAB 5 DNYT 4 DMAREQMODE 3 OUTCOUNT bytes in EP0/1 OUT FIFO 16-bit OUTCOUNT
0x18
 FIFO_EP0 FIFO_EP0
0x20
 FIFO_EP1 FIFO_EP1
0x24
 FIFO_EP2 FIFO_EP2
0x28
 EPINFO Endpoint information EPINFO
0x78
 RAMINFO RAM information RAMINFO
0x79
 INTR DMA pending interrupts INTR
0x200
 CNTL DMA control bits CNTL 1
0x204
0x214
 BURST 9 2 0 0x0 4 0x1 8 0x2 16 0x3 INTR_EN 3 MODE_1 2 DIR_IN 1 ENA 0 ADDR DMA channel 2 AHB memory addr ADDR 1
0x208
0x218
 COUNT DMA channel 2 byte count COUNT 1
0x20c
0x21c
 BDMAC BDMAC (BCH & NAND DMA Controller) BDMAC
0xb3450000
 DSA DMA source address DSA 0 3 (0x00 + (n) * 0x20) DTA DMA target address DTA 0 3 (0x04 + (n) * 0x20) DTC DMA transfer count DTC 0 3 (0x08 + (n) * 0x20) DRT BDMA request source register DRT 0 3 (0x0c + (n) * 0x20) RS 0 6 BCH_ENC 0x2 BCH_DEC 0x3 NAND0 0x6 NAND1 0x7 AUTO 0x8 EXT 0xc DCS BDMA channel control/status register DCS 0 3 (0x10 + (n) * 0x20) NDES descriptor (0) or not (1) ? 31 DES8 Descriptor 8 Word 30 LASTMD1 BCH Decoding last mode 1, there's two descriptor for decoding blcok 28 CDOA copy of DMA offset address 16 8 BERR BCH error within this transfer, Only for channel 0 7 5 BUERR BCH uncorrectable error, only for channel 0 6 NSERR status error, only for channel 1 5 AR address error 4 TT transfer terminated 3 HLT DMA halted 2 BAC BCH auto correction 1 EN channel enable bit 0 DCM BDMA channel command register DCM 0 3 (0x14 + (n) * 0x20) EACKS_LOW External DACK Output Level Select, active low 31 EACKM_WRITE External DACK Output Mode Select, output in write cycle 30 ERDM External DREQ Detection Mode Select 28 2 LOW 0x0 FALL 0x1 HIGH 0x2 RISE 0x3 BLAST BCH last 25 SAI source address increment 23 DAI dest address increment 22 SWDH source port width 14 2 32 0x0 8 0x1 16 0x2 DWDH dest port width 12 2 32 0x0 8 0x1 16 0x2 DS transfer data size of a data unit 8 3 32BIT 0x0 8BIT 0x1 16BIT 0x2 16BYTE 0x3 32BYTE 0x4 64BYTE 0x5 NRD NAND direct read 7 NWR NAND direct write 6 NAC NAND AL/CL enable 5 STDE Stride Disable/Enable 2 TIE DMA transfer interrupt enable 1 LINK descriptor link enable 0 DDA BDMA descriptor address register DDA 0 3 (0x18 + (n) * 0x20) BASE descriptor base address 12 20 OFFSET descriptor offset address 4 8 DSD BDMA stride address register DSD 0 3 (0x1c + (n) * 0x20) TSD target stride address 16 16 SSD source stride address 0 16 DNT BDMA NAND Detect timer register DNT 0 3 (0xc0 + (n) * 0x04) DTCT tail counter 16 7 DNTE enable detect timer 15 DNT detect counter 0 6 DMAC BDMA control register DMAC
0x300
 PR channel priority mode 8 2 01_2 0x0 12_0 0x1 20_1 0x2 012 0x3 HLT DMA halt flag 3 AR address error flag 2 DMAE DMA enable bit 0 DIRQP BDMA interrupt pending register DIRQP
0x304
 CIRQ2 irq pending status for channel 2 2 CIRQ1 irq pending status for channel 1 1 CIRQ0 irq pending status for channel 0 0 DDR BDMA doorbell register DDR
0x308
 DB2 doorbell for channel 2 2 DB1 doorbell for channel 1 1 DB0 doorbell for channel 0 0 DDRS BDMA doorbell set register DDRS
0x30c
 DBS2 enable doorbell for channel 2 2 DBS1 enable doorbell for channel 1 1 DBS0 enable doorbell for channel 0 0 DCKE DMA clock enable DCKE
0x310
 DCKES DCKES
0x314
 DCKEC DCKEC
0x318
 GPS GPS
0xb3480000
 ETHC ETHC
0xb34b0000
 BCH BCH
0xb34d0000
 CTRL BCH Control register CTRL
0x0
 DMAE BCH DMA Enable 7 BSEL 24 Bit BCH Select 3 3 4 0x0 8 0x1 12 0x2 16 0x3 20 0x4 24 0x5 ENCE BCH Encoding Select 2 BRST BCH Reset 1 BCHE BCH Enable 0 set 4 clr 8 COUNT BCH ENC/DEC Count Register COUNT
0xc
 DEC 16 11 ENC 0 11 DATA BCH data register DATA
0x10
 8 PARITY BCH Parity register PARITY 0 12 0x14 + 4 *(n) ERROR BCH Error Report Register ERROR 0 12 0x3C + 4*(n) INDEX_ODD 16 13 INDEX_EVEN 0 13 INTS BCH Interrupt Status Register INTS
0x6c
 ERRC 27 5 ALL0 5 ALLf 4 DECF 3 ENCF 2 UNCOR 1 ERR 0 INTE BCH Interrupt Enable register INTE
0x70