stmp3700
STMP3700
Amaury Pouly
2.4.0
APBH
APHB DMA
AHB-to-APBH Bridge with DMA
APBH
0x80004000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RESET_CHANNEL
16
8
SSP1
0x1
SSP2
0x2
LCDIF
0x4
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x40
NAND3
0x80
CLKGATE_CHANNEL
8
8
SSP1
0x1
SSP2
0x2
LCDIF
0x4
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x40
NAND3
0x80
FREEZE_CHANNEL
0
8
SSP1
0x1
SSP2
0x2
LCDIF
0x4
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x30
NAND3
0x40
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
CH_AHB_ERROR_IRQ
16
8
CH_CMDCMPLT_IRQ_EN
8
8
CH_CMDCMPLT_IRQ
0
8
set
4
clr
8
tog
12
DEVSEL
DEVSEL
0x20
CH7
28
4
CH6
24
4
CH5
20
4
CH4
16
4
CH3
12
4
CH2
8
4
CH1
4
4
CH0
0
4
CHn_CURCMDAR
CHn_CURCMDAR
0
8
0x40
0x70
CMD_ADDR
0
32
CHn_NXTCMDAR
CHn_NXTCMDAR
0
8
0x50
0x70
CMD_ADDR
0
32
CHn_CMD
CHn_CMD
0
8
0x60
0x70
XFER_COUNT
16
16
CMDWORDS
12
4
HALTONTERMINATE
8
WAIT4ENDCMD
7
SEMAPHORE
6
NANDWAIT4READY
5
NANDLOCK
4
IRQONCMPLT
3
CHAIN
2
COMMAND
0
2
NO_DMA_XFER
0x0
DMA_WRITE
0x1
DMA_READ
0x2
DMA_SENSE
0x3
CHn_BAR
CHn_BAR
0
8
0x70
0x70
ADDRESS
0
32
CHn_SEMA
CHn_SEMA
0
8
0x80
0x70
PHORE
16
8
INCREMENT_SEMA
0
8
CHn_DEBUG1
CHn_DEBUG1
0
8
0x90
0x70
REQ
31
BURST
30
KICK
29
END
28
NEXTCMDADDRVALID
24
RD_FIFO_EMPTY
23
RD_FIFO_FULL
22
WR_FIFO_EMPTY
21
WR_FIFO_FULL
20
STATEMACHINE
0
5
IDLE
0x0
REQ_CMD1
0x1
REQ_CMD3
0x2
REQ_CMD2
0x3
XFER_DECODE
0x4
REQ_WAIT
0x5
REQ_CMD4
0x6
PIO_REQ
0x7
READ_FLUSH
0x8
READ_WAIT
0x9
WRITE
0xc
READ_REQ
0xd
CHECK_CHAIN
0xe
XFER_COMPLETE
0xf
WAIT_END
0x15
WRITE_WAIT
0x1c
CHECK_WAIT
0x1e
CHn_DEBUG2
CHn_DEBUG2
0
8
0xa0
0x70
APB_BYTES
16
16
AHB_BYTES
0
16
VERSION
VERSION
0x3f0
MAJOR
24
8
MINOR
16
8
STEP
0
16
APBX
APHX DMA
AHB-to-APBX Bridge with DMA
APBX
0x80024000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RESET_CHANNEL
16
8
AUDIOIN
0x1
AUDIOOUT
0x2
SPDIF_TX
0x4
SAIF2
0x4
I2C
0x8
SAIF1
0x10
DRI
0x20
UART_RX
0x40
IRDA_RX
0x40
UART_TX
0x80
IRDA_TX
0x80
FREEZE_CHANNEL
0
8
AUDIOIN
0x1
AUDIOOUT
0x2
SPDIF_TX
0x4
SAIF2
0x4
I2C
0x8
SAIF1
0x10
DRI
0x20
UART_RX
0x40
IRDA_RX
0x40
UART_TX
0x80
IRDA_TX
0x80
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
CH_AHB_ERROR_IRQ
16
8
CH_CMDCMPLT_IRQ_EN
8
8
CH_CMDCMPLT_IRQ
0
8
set
4
clr
8
tog
12
DEVSEL
DEVSEL
0x20
CH7
28
4
USE_UART
0x0
USE_IRDA
0x1
CH6
24
4
USE_UART
0x0
USE_IRDA
0x1
CH5
20
4
CH4
16
4
CH3
12
4
CH2
8
4
USE_SPDIF
0x0
USE_SAIF2
0x1
CH1
4
4
CH0
0
4
CHn_CURCMDAR
CHn_CURCMDAR
0
8
0x40
0x70
CMD_ADDR
0
32
CHn_NXTCMDAR
CHn_NXTCMDAR
0
8
0x50
0x70
CMD_ADDR
0
32
CHn_CMD
CHn_CMD
0
8
0x60
0x70
XFER_COUNT
16
16
CMDWORDS
12
4
WAIT4ENDCMD
7
SEMAPHORE
6
IRQONCMPLT
3
CHAIN
2
COMMAND
0
2
NO_DMA_XFER
0x0
DMA_WRITE
0x1
DMA_READ
0x2
CHn_BAR
CHn_BAR
0
8
0x70
0x70
ADDRESS
0
32
CHn_SEMA
CHn_SEMA
0
8
0x80
0x70
PHORE
16
8
INCREMENT_SEMA
0
8
CHn_DEBUG1
CHn_DEBUG1
0
8
0x90
0x70
REQ
31
BURST
30
KICK
29
END
28
NEXTCMDADDRVALID
24
RD_FIFO_EMPTY
23
RD_FIFO_FULL
22
WR_FIFO_EMPTY
21
WR_FIFO_FULL
20
STATEMACHINE
0
5
IDLE
0x0
REQ_CMD1
0x1
REQ_CMD3
0x2
REQ_CMD2
0x3
XFER_DECODE
0x4
REQ_WAIT
0x5
REQ_CMD4
0x6
PIO_REQ
0x7
READ_FLUSH
0x8
READ_WAIT
0x9
WRITE
0xc
READ_REQ
0xd
CHECK_CHAIN
0xe
XFER_COMPLETE
0xf
WAIT_END
0x15
WRITE_WAIT
0x1c
CHECK_WAIT
0x1e
CHn_DEBUG2
CHn_DEBUG2
0
8
0xa0
0x70
APB_BYTES
16
16
AHB_BYTES
0
16
VERSION
VERSION
0x3f0
MAJOR
24
8
MINOR
16
8
STEP
0
16
AUDIOIN
AUDIOIN/ADC
Digital Audio Filter Input
AUDIOIN
0x8004c000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
LR_SWAP
10
EDGE_SYNC
9
INVERT_1BIT
8
OFFSET_ENABLE
7
HPF_ENABLE
6
WORD_LENGTH
5
LOOPBACK
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
ADC_PRESENT
31
ADCSRR
ADCSRR
0x20
OSR
31
OSR6
0x0
OSR12
0x1
BASEMULT
28
3
SINGLE_RATE
0x1
DOUBLE_RATE
0x2
QUAD_RATE
0x4
SRC_HOLD
24
3
SRC_INT
16
5
SRC_FRAC
0
13
set
4
clr
8
tog
12
ADCVOLUME
ADCVOLUME
0x30
VOLUME_UPDATE_LEFT
28
EN_ZCD
25
VOLUME_LEFT
16
8
VOLUME_UPDATE_RIGHT
12
VOLUME_RIGHT
0
8
set
4
clr
8
tog
12
ADCDEBUG
ADCDEBUG
0x40
ENABLE_ADCDMA
31
ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
3
SET_INTERRUPT3_HAND_SHAKE
2
DMA_PREQ
1
FIFO_STATUS
0
set
4
clr
8
tog
12
ADCVOL
ADCVOL
0x50
VOLUME_UPDATE_PENDING
28
EN_ADC_ZCD
25
MUTE
24
SELECT_LEFT
12
2
GAIN_LEFT
8
4
SELECT_RIGHT
4
2
GAIN_RIGHT
0
4
set
4
clr
8
tog
12
MICLINE
MICLINE
0x60
DIVIDE_LINE1
29
DIVIDE_LINE2
28
MIC_SELECT
24
MIC_RESISTOR
20
2
Off
0x0
2KOhm
0x1
4KOhm
0x2
8KOhm
0x3
MIC_BIAS
16
3
MIC_CHOPCLK
4
2
MIC_GAIN
0
2
0dB
0x0
20dB
0x1
30dB
0x2
40dB
0x3
set
4
clr
8
tog
12
ANACLKCTRL
ANACLKCTRL
0x70
CLKGATE
31
DITHER_OFF
6
SLOW_DITHER
5
INVERT_ADCCLK
4
ADCDIV
0
3
set
4
clr
8
tog
12
DATA
DATA
0x80
HIGH
16
16
LOW
0
16
AUDIOOUT
AUDIOOUT/DAC
Digital Audio Filter Output
AUDIOOUT
0x80048000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
LR_SWAP
14
EDGE_SYNC
13
INVERT_1BIT
12
SS3D_EFFECT
8
2
WORD_LENGTH
6
DAC_ZERO_ENABLE
5
LOOPBACK
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
DAC_PRESENT
31
DACSRR
DACSRR
0x20
OSR
31
OSR6
0x0
OSR12
0x1
BASEMULT
28
3
SINGLE_RATE
0x1
DOUBLE_RATE
0x2
QUAD_RATE
0x4
SRC_HOLD
24
3
SRC_INT
16
5
SRC_FRAC
0
13
set
4
clr
8
tog
12
DACVOLUME
DACVOLUME
0x30
VOLUME_UPDATE_LEFT
28
EN_ZCD
25
MUTE_LEFT
24
VOLUME_LEFT
16
8
VOLUME_UPDATE_RIGHT
12
MUTE_RIGHT
8
VOLUME_RIGHT
0
8
set
4
clr
8
tog
12
DACDEBUG
DACDEBUG
0x40
ENABLE_DACDMA
31
RAM_SS
8
4
SET_INTERRUPT1_CLK_CROSS
5
SET_INTERRUPT0_CLK_CROSS
4
SET_INTERRUPT1_HAND_SHAKE
3
SET_INTERRUPT0_HAND_SHAKE
2
DMA_PREQ
1
FIFO_STATUS
0
set
4
clr
8
tog
12
HPVOL
HPVOL
0x50
VOLUME_UPDATE_PENDING
28
EN_MSTR_ZCD
25
MUTE
24
SELECT
16
VOL_LEFT
8
7
VOL_RIGHT
0
7
set
4
clr
8
tog
12
RESERVED
RESERVED
0x60
PWRDN
PWRDN
0x70
LINEOUT
24
SELFBIAS
20
RIGHT_ADC
16
DAC
12
ADC
8
CAPLESS
4
HEADPHONE
0
set
4
clr
8
tog
12
REFCTRL
REFCTRL
0x80
FASTSETTLING
26
RAISE_REF
25
XTAL_BGR_BIAS
24
VBG_ADJ
20
3
LOW_PWR
19
LW_REF
18
BIAS_CTRL
16
2
VDDXTAL_TO_VDDD
14
ADJ_ADC
13
ADJ_VAG
12
ADC_REFVAL
8
4
VAG_VAL
4
4
DAC_ADJ
0
3
set
4
clr
8
tog
12
ANACTRL
ANACTRL
0x90
SHORT_CM_STS
28
SHORT_LR_STS
24
SHORTMODE_CM
20
2
SHORTMODE_LR
17
2
SHORT_LVLADJL
12
3
SHORT_LVLADJR
8
3
HP_HOLD_GND
5
HP_CLASSAB
4
set
4
clr
8
tog
12
TEST
TEST
0xa0
HP_ANTIPOP
28
3
TM_ADCIN_TOHP
26
TM_LINEOUT
25
TM_HPCOMMON
24
HP_I1_ADJ
22
2
HP_IALL_ADJ
20
2
VAG_CLASSA
13
VAG_DOUBLE_I
12
DAC_CLASSA
2
DAC_DOUBLE_I
1
DAC_DIS_RTZ
0
set
4
clr
8
tog
12
BISTCTRL
BISTCTRL
0xb0
FAIL
3
PASS
2
DONE
1
START
0
set
4
clr
8
tog
12
BISTSTAT0
BISTSTAT0
0xc0
DATA
0
24
BISTSTAT1
BISTSTAT1
0xd0
STATE
24
5
ADDR
0
8
ANACLKCTRL
ANACLKCTRL
0xe0
CLKGATE
31
INVERT_DACCLK
4
DACDIV
0
3
set
4
clr
8
tog
12
DATA
DATA
0xf0
HIGH
16
16
LOW
0
16
set
4
clr
8
tog
12
LINEOUTCTRL
LINEOUTCTRL
0x100
VOLUME_UPDATE_PENDING
28
EN_LINEOUT_ZCD
25
MUTE
24
VAG_CTRL
20
4
OUT_CURRENT
16
4
CHARGE_CAP
13
3
VOLUME_LEFT
8
5
VOLUME_RIGHT
0
5
set
4
clr
8
tog
12
VERSION
VERSION
0x200
MAJOR
24
8
MINOR
16
8
STEP
0
16
CLKCTRL
Clock Controller
Clock Generation and Control
CLKCTRL
0x80040000
PLLCTRL0
PLLCTRL0
0x0
LFR_SEL
28
2
DEFAULT
0x0
TIMES_2
0x1
TIMES_05
0x2
UNDEFINED
0x3
CP_SEL
24
2
DEFAULT
0x0
TIMES_2
0x1
TIMES_05
0x2
UNDEFINED
0x3
DIV_SEL
20
2
DEFAULT
0x0
LOWER
0x1
LOWEST
0x2
UNDEFINED
0x3
EN_USB_CLKS
18
POWER
16
set
4
clr
8
tog
12
PLLCTRL1
PLLCTRL1
0x10
LOCK
31
FORCE_LOCK
30
LOCK_COUNT
0
16
CPU
CPU
0x20
BUSY_REF_XTAL
29
BUSY_REF_CPU
28
DIV_XTAL_FRAC_EN
26
DIV_XTAL
16
10
INTERRUPT_WAIT
12
DIV_CPU_FRAC_EN
10
DIV_CPU
0
10
set
4
clr
8
tog
12
HBUS
HBUS
0x30
BUSY
29
APBHDMA_AS_ENABLE
26
APBXDMA_AS_ENABLE
25
TRAFFIC_JAM_AS_ENABLE
24
TRAFFIC_AS_ENABLE
23
CPU_DATA_AS_ENABLE
22
CPU_INSTR_AS_ENABLE
21
AUTO_SLOW_MODE
20
SLOW_DIV
16
3
BY1
0x0
BY2
0x1
BY4
0x2
BY8
0x3
BY16
0x4
BY32
0x5
DIV_FRAC_EN
5
DIV
0
5
set
4
clr
8
tog
12
XBUS
XBUS
0x40
BUSY
31
DIV_FRAC_EN
10
DIV
0
10
XTAL
XTAL
0x50
UART_CLK_GATE
31
FILT_CLK24M_GATE
30
PWM_CLK24M_GATE
29
DRI_CLK24M_GATE
28
DIGCTRL_CLK1M_GATE
27
TIMROT_CLK32K_GATE
26
DIV_UART
0
2
set
4
clr
8
tog
12
PIX
PIX
0x60
CLKGATE
31
BUSY
29
DIV_FRAC_EN
15
DIV
0
15
SSP
SSP
0x70
CLKGATE
31
BUSY
29
DIV_FRAC_EN
9
DIV
0
9
GPMI
GPMI
0x80
CLKGATE
31
BUSY
29
DIV_FRAC_EN
10
DIV
0
10
SPDIF
SPDIF
0x90
CLKGATE
31
EMI
EMI
0xa0
CLKGATE
31
BUSY_REF_XTAL
29
BUSY_REF_EMI
28
BUSY_DCC_RESYNC
17
DCC_RESYNC_ENABLE
16
DIV_XTAL
8
4
DIV_EMI
0
6
IR
IR
0xb0
CLKGATE
31
AUTO_DIV
29
IR_BUSY
28
IROV_BUSY
27
IROV_DIV
16
9
IR_DIV
0
10
SAIF
SAIF
0xc0
CLKGATE
31
BUSY
29
DIV_FRAC_EN
16
DIV
0
16
FRAC
FRAC
0xd0
CLKGATEIO
31
IO_STABLE
30
IOFRAC
24
6
CLKGATEPIX
23
PIX_STABLE
22
PIXFRAC
16
6
CLKGATEEMI
15
EMI_STABLE
14
EMIFRAC
8
6
CLKGATECPU
7
CPU_STABLE
6
CPUFRAC
0
6
set
4
clr
8
tog
12
CLKSEQ
CLKSEQ
0xe0
BYPASS_CPU
7
BYPASS_EMI
6
BYPASS_SSP
5
BYPASS_GPMI
4
BYPASS_IR
3
BYPASS_PIX
1
BYPASS_SAIF
0
set
4
clr
8
tog
12
RESET
RESET
0xf0
CHIP
1
DIG
0
VERSION
VERSION
0x100
MAJOR
24
8
MINOR
16
8
STEP
0
16
DCP
Data CoProcessor
Data Co-Processor (DCP)
DCP
0x80028000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PRESENT_CRYPTO
29
Present
0x1
Absent
0x0
PRESENT_CSC
28
Present
0x1
Absent
0x0
GATHER_RESIDUAL_WRITES
23
ENABLE_CONTEXT_CACHING
22
ENABLE_CONTEXT_SWITCHING
21
CSC_INTERRUPT_ENABLE
8
CHANNEL_INTERRUPT_ENABLE
0
8
CH0
0x1
CH1
0x2
CH2
0x4
CH3
0x8
set
4
clr
8
tog
12
STAT
STAT
0x10
OTP_KEY_READY
28
CUR_CHANNEL
24
4
None
0x0
CH0
0x1
CH1
0x2
CH2
0x3
CH3
0x4
CSC
0x8
READY_CHANNELS
16
8
CH0
0x1
CH1
0x2
CH2
0x4
CH3
0x8
CSCIRQ
8
IRQ
0
4
set
4
clr
8
tog
12
CHANNELCTRL
CHANNELCTRL
0x20
CSC_PRIORITY
17
2
HIGH
0x3
MED
0x2
LOW
0x1
BACKGROUND
0x0
CH0_IRQ_MERGED
16
HIGH_PRIORITY_CHANNEL
8
8
CH0
0x1
CH1
0x2
CH2
0x4
CH3
0x8
ENABLE_CHANNEL
0
8
CH0
0x1
CH1
0x2
CH2
0x4
CH3
0x8
set
4
clr
8
tog
12
CAPABILITY0
CAPABILITY0
0x30
NUM_CHANNELS
8
4
NUM_KEYS
0
8
CAPABILITY1
CAPABILITY1
0x40
HASH_ALGORITHMS
16
16
SHA1
0x1
CRC32
0x2
CIPHER_ALGORITHMS
0
16
AES128
0x1
CONTEXT
CONTEXT
0x50
ADDR
0
32
KEY
KEY
0x60
INDEX
4
2
SUBWORD
0
2
KEYDATA
KEYDATA
0x70
DATA
0
32
PACKET0
PACKET0
0x80
ADDR
0
32
PACKET1
PACKET1
0x90
TAG
24
8
OUTPUT_WORDSWAP
23
OUTPUT_BYTESWAP
22
INPUT_WORDSWAP
21
INPUT_BYTESWAP
20
KEY_WORDSWAP
19
KEY_BYTESWAP
18
TEST_SEMA_IRQ
17
CONSTANT_FILL
16
HASH_OUTPUT
15
INPUT
0x0
OUTPUT
0x1
CHECK_HASH
14
HASH_TERM
13
HASH_INIT
12
PAYLOAD_KEY
11
OTP_KEY
10
CIPHER_INIT
9
CIPHER_ENCRYPT
8
ENCRYPT
0x1
DECRYPT
0x0
ENABLE_BLIT
7
ENABLE_HASH
6
ENABLE_CIPHER
5
ENABLE_MEMCOPY
4
CHAIN_CONTIGUOUS
3
CHAIN
2
DECR_SEMAPHORE
1
INTERRUPT
0
PACKET2
PACKET2
0xa0
CIPHER_CFG
24
8
HASH_SELECT
16
4
SHA1
0x0
CRC32
0x1
KEY_SELECT
8
8
CIPHER_MODE
4
4
ECB
0x0
CCB
0x1
CIPHER_SELECT
0
4
AES128
0x0
PACKET3
PACKET3
0xb0
ADDR
0
32
PACKET4
PACKET4
0xc0
ADDR
0
32
PACKET5
PACKET5
0xd0
COUNT
0
32
PACKET6
PACKET6
0xe0
ADDR
0
32
CHnCMDPTR
CHnCMDPTR
0
4
0x100
0x40
ADDR
0
32
CHnSEMA
CHnSEMA
0
4
0x110
0x40
VALUE
16
8
INCREMENT
0
8
CHnSTAT
CHnSTAT
0
4
0x120
0x40
TAG
24
8
ERROR_CODE
16
8
NEXT_CHAIN_IS_0
0x1
NO_CHAIN
0x2
CONTEXT_ERROR
0x3
PAYLOAD_ERROR
0x4
INVALID_MODE
0x5
ERROR_DST
5
ERROR_SRC
4
ERROR_PACKET
3
ERROR_SETUP
2
HASH_MISMATCH
1
set
4
clr
8
tog
12
CHnOPTS
CHnOPTS
0
4
0x130
0x40
RECOVERY_TIMER
0
16
set
4
clr
8
tog
12
CSCCTRL0
CSCCTRL0
0x300
UPSAMPLE
14
SCALE
13
ROTATE
12
SUBSAMPLE
11
DELTA
10
RGB_FORMAT
8
2
RGB16_565
0x0
RGB24
0x2
YUV422I
0x3
YUV_FORMAT
4
4
YUV420
0x0
YUV422
0x2
ENABLE
0
set
4
clr
8
tog
12
CSCSTAT
CSCSTAT
0x310
ERROR_CODE
16
8
LUMA0_FETCH_ERROR_Y0
0x1
LUMA1_FETCH_ERROR_Y1
0x2
CHROMA_FETCH_ERROR_U
0x3
CHROMA_FETCH_ERROR_V
0x4
ERROR_DST
5
ERROR_SRC
4
ERROR_SETUP
2
COMPLETE
0
set
4
clr
8
tog
12
CSCOUTBUFPARAM
CSCOUTBUFPARAM
0x320
FIELD_SIZE
12
12
LINE_SIZE
0
12
CSCINBUFPARAM
CSCINBUFPARAM
0x330
LINE_SIZE
0
12
CSCRGB
CSCRGB
0x340
ADDR
0
32
CSCLUMA
CSCLUMA
0x350
ADDR
0
32
CSCCHROMAU
CSCCHROMAU
0x360
ADDR
0
32
CSCCHROMAV
CSCCHROMAV
0x370
ADDR
0
32
CSCCOEFF0
CSCCOEFF0
0x380
C0
16
10
UV_OFFSET
8
8
Y_OFFSET
0
8
CSCCOEFF1
CSCCOEFF1
0x390
C1
16
10
C4
0
10
CSCCOEFF2
CSCCOEFF2
0x3a0
C2
16
10
C3
0
10
CSCXSCALE
CSCXSCALE
0x3e0
INT
24
2
FRAC
12
12
WIDTH
0
12
CSCYSCALE
CSCYSCALE
0x3f0
INT
24
2
FRAC
12
12
HEIGHT
0
12
DBGSELECT
DBGSELECT
0x400
INDEX
0
8
CONTROL
0x1
OTPKEY0
0x10
OTPKEY1
0x11
OTPKEY2
0x12
OTPKEY3
0x13
DBGDATA
DBGDATA
0x410
DATA
0
32
VERSION
VERSION
0x420
MAJOR
24
8
MINOR
16
8
STEP
0
16
DIGCTL
Digital Control
Digital Control and On-Chip RAM
DIGCTL
0x8001c000
CTRL
CTRL
0x0
TRAP_IRQ
29
DCP_BIST_CLKEN
23
DCP_BIST_START
22
ARM_BIST_CLKEN
21
USB_TESTMODE
20
ANALOG_TESTMODE
19
DIGITAL_TESTMODE
18
ARM_BIST_START
17
UART_LOOPBACK
16
NORMAL
0x0
LOOPIT
0x1
SAIF_LOOPBACK
15
NORMAL
0x0
LOOPIT
0x1
SAIF_CLKMUX_SEL
13
2
MBL_CLK_OUT
0x0
BL_CLK_OUT
0x1
M_CLK_OUT_BL_CLK_IN
0x2
BL_CLK_IN
0x3
SAIF_CLKMST_SEL
12
SAIF1_MST
0x0
SAIF2_MST
0x1
SAIF_ALT_BITCLK_SEL
11
USE_SERIAL_JTAG
6
OLD_JTAG
0x0
SERIAL_JTAG
0x1
TRAP_IN_RANGE
5
TRAP_ENABLE
4
DEBUG_DISABLE
3
USB_CLKGATE
2
RUN
0x0
NO_CLKS
0x1
JTAG_SHIELD
1
NORMAL
0x0
SHIELDS_UP
0x1
LATCH_ENTROPY
0
set
4
clr
8
tog
12
STATUS
STATUS
0x10
USB_HS_PRESENT
31
USB_OTG_PRESENT
30
USB_HOST_PRESENT
29
USB_DEVICE_PRESENT
28
DCP_BIST_FAIL
10
DCP_BIST_PASS
9
DCP_BIST_DONE
8
JTAG_IN_USE
4
PACKAGE_TYPE
1
3
WRITTEN
0
HCLKCOUNT
HCLKCOUNT
0x20
COUNT
0
32
RAMCTRL
RAMCTRL
0x30
SPEED_SELECT
8
4
RAM_REPAIR_EN
0
set
4
clr
8
tog
12
RAMREPAIR
RAMREPAIR
0x40
ADDR
0
16
set
4
clr
8
tog
12
ROMCTRL
ROMCTRL
0x50
RD_MARGIN
0
4
set
4
clr
8
tog
12
WRITEONCE
WRITEONCE
0x60
BITS
0
32
ENTROPY
ENTROPY
0x90
VALUE
0
32
ENTROPY_LATCHED
ENTROPY_LATCHED
0xa0
VALUE
0
32
SJTAGDBG
SJTAGDBG
0xb0
SJTAG_STATE
16
11
SJTAG_TDO
10
SJTAG_TDI
9
SJTAG_MODE
8
DELAYED_ACTIVE
4
4
ACTIVE
3
SJTAG_PIN_STATE
2
SJTAG_DEBUG_DATA
1
SJTAG_DEBUG_OE
0
set
4
clr
8
tog
12
MICROSECONDS
MICROSECONDS
0xc0
VALUE
0
32
set
4
clr
8
tog
12
DBGRD
DBGRD
0xd0
COMPLEMENT
0
32
DBG
DBG
0xe0
VALUE
0
32
OCRAM_BIST_CSR
OCRAM_BIST_CSR
0xf0
BIST_DATA_CHANGE
9
BIST_CLKEN
8
FAIL
3
PASS
2
DONE
1
START
0
set
4
clr
8
tog
12
OCRAM_STATUS0
OCRAM_STATUS0
0x110
FAILDATA00
0
32
OCRAM_STATUS1
OCRAM_STATUS1
0x120
FAILDATA01
0
32
OCRAM_STATUS2
OCRAM_STATUS2
0x130
FAILDATA10
0
32
OCRAM_STATUS3
OCRAM_STATUS3
0x140
FAILDATA11
0
32
OCRAM_STATUS4
OCRAM_STATUS4
0x150
FAILDATA20
0
32
OCRAM_STATUS5
OCRAM_STATUS5
0x160
FAILDATA21
0
32
OCRAM_STATUS6
OCRAM_STATUS6
0x170
FAILDATA30
0
32
OCRAM_STATUS7
OCRAM_STATUS7
0x180
FAILDATA31
0
32
OCRAM_STATUS8
OCRAM_STATUS8
0x190
FAILADDR01
16
16
FAILADDR00
0
16
OCRAM_STATUS9
OCRAM_STATUS9
0x1a0
FAILADDR11
16
16
FAILADDR10
0
16
OCRAM_STATUS10
OCRAM_STATUS10
0x1b0
FAILADDR21
16
16
FAILADDR20
0
16
OCRAM_STATUS11
OCRAM_STATUS11
0x1c0
FAILADDR31
16
16
FAILADDR30
0
16
OCRAM_STATUS12
OCRAM_STATUS12
0x1d0
FAILSTATE11
24
5
FAILSTATE10
16
5
FAILSTATE01
8
5
FAILSTATE00
0
5
OCRAM_STATUS13
OCRAM_STATUS13
0x1e0
FAILSTATE31
24
5
FAILSTATE30
16
5
FAILSTATE21
8
5
FAILSTATE20
0
5
SCRATCH0
SCRATCH0
0x290
PTR
0
32
SCRATCH1
SCRATCH1
0x2a0
PTR
0
32
ARMCACHE
ARMCACHE
0x2b0
CACHE_SS
8
2
DTAG_SS
4
2
ITAG_SS
0
2
DEBUG_TRAP_ADDR_LOW
DEBUG_TRAP_ADDR_LOW
0x2c0
ADDR
0
32
DEBUG_TRAP_ADDR_HIGH
DEBUG_TRAP_ADDR_HIGH
0x2d0
ADDR
0
32
SGTL
SGTL
0x300
COPYRIGHT
0
32
CHIPID
CHIPID
0x310
PRODUCT_CODE
16
16
REVISION
0
8
AHB_STATS_SELECT
AHB_STATS_SELECT
0x330
L3_MASTER_SELECT
24
4
APBH
0x1
APBX
0x2
USB
0x4
L2_MASTER_SELECT
16
4
ARM_D
0x1
L1_MASTER_SELECT
8
4
ARM_I
0x1
L0_MASTER_SELECT
0
4
ECC8
0x1
CRYPTO
0x2
L0_AHB_ACTIVE_CYCLES
L0_AHB_ACTIVE_CYCLES
0x340
COUNT
0
32
L0_AHB_DATA_STALLED
L0_AHB_DATA_STALLED
0x350
COUNT
0
32
L0_AHB_DATA_CYCLES
L0_AHB_DATA_CYCLES
0x360
COUNT
0
32
L1_AHB_ACTIVE_CYCLES
L1_AHB_ACTIVE_CYCLES
0x370
COUNT
0
32
L1_AHB_DATA_STALLED
L1_AHB_DATA_STALLED
0x380
COUNT
0
32
L1_AHB_DATA_CYCLES
L1_AHB_DATA_CYCLES
0x390
COUNT
0
32
L2_AHB_ACTIVE_CYCLES
L2_AHB_ACTIVE_CYCLES
0x3a0
COUNT
0
32
L2_AHB_DATA_STALLED
L2_AHB_DATA_STALLED
0x3b0
COUNT
0
32
L2_AHB_DATA_CYCLES
L2_AHB_DATA_CYCLES
0x3c0
COUNT
0
32
L3_AHB_ACTIVE_CYCLES
L3_AHB_ACTIVE_CYCLES
0x3d0
COUNT
0
32
L3_AHB_DATA_STALLED
L3_AHB_DATA_STALLED
0x3e0
COUNT
0
32
L3_AHB_DATA_CYCLES
L3_AHB_DATA_CYCLES
0x3f0
COUNT
0
32
MPTEn_LOC
MPTEn_LOC
0
16
0x400
0x10
LOC
0
12
EMICLK_DELAY
EMICLK_DELAY
0x480
NUM_TAPS
0
5
DRAM
DRAM Registers
DRAM Registers
DRAM
0x800e0000
CTL00
CTL00
0x0
AHB0_W_PRIORITY
24
AHB0_R_PRIORITY
16
AHB0_FIFO_TYPE_REG
8
ADDR_CMP_EN
0
CTL01
CTL01
0x4
AHB2_FIFO_TYPE_REG
24
AHB1_W_PRIORITY
16
AHB1_R_PRIORITY
8
AHB1_FIFO_TYPE_REG
0
CTL02
CTL02
0x8
AHB3_R_PRIORITY
24
AHB3_FIFO_TYPE_REG
16
AHB2_W_PRIORITY
8
AHB2_R_PRIORITY
0
CTL03
CTL03
0xc
AUTO_REFRESH_MODE
24
AREFRESH
16
AP
8
AHB3_W_PRIORITY
0
CTL04
CTL04
0x10
DLL_BYPASS_MODE
24
DLLLOCKREG
16
CONCURRENTAP
8
BANK_SPLIT_EN
0
CTL05
CTL05
0x14
INTRPTREADA
24
INTRPTAPBURST
16
FAST_WRITE
8
EN_LOWPOWER_MODE
0
CTL06
CTL06
0x18
POWER_DOWN
24
PLACEMENT_EN
16
NO_CMD_INIT
8
INTRPTWRITEA
0
CTL07
CTL07
0x1c
RW_SAME_EN
24
REG_DIMM_ENABLE
16
RD2RD_TURN
8
PRIORITY_EN
0
CTL08
CTL08
0x20
TRAS_LOCKOUT
24
START
16
SREFRESH
8
SDR_MODE
0
CTL09
CTL09
0x24
OUT_OF_RANGE_TYPE
24
2
OUT_OF_RANGE_SOURCE_ID
16
2
WRITE_MODEREG
8
WRITEINTERP
0
CTL10
CTL10
0x28
AGE_COUNT
24
3
ADDR_PINS
16
3
TEMRS
8
2
Q_FULLNESS
0
2
CTL11
CTL11
0x2c
MAX_CS_REG
24
3
COMMAND_AGE_COUNT
16
3
COLUMN_SIZE
8
3
CASLAT
0
3
CTL12
CTL12
0x30
TWR_INT
24
3
TRRD
16
3
TCKE
0
3
CTL13
CTL13
0x34
CASLAT_LIN_GATE
24
4
CASLAT_LIN
16
4
APREBIT
8
4
TWTR
0
3
CTL14
CTL14
0x38
MAX_COL_REG
24
4
LOWPOWER_REFRESH_ENABLE
16
4
INITAREF
8
4
CS_MAP
0
4
CTL15
CTL15
0x3c
TRP
24
4
TDAL
16
4
PORT_BUSY
8
4
MAX_ROW_REG
0
4
CTL16
CTL16
0x40
TMRD
24
5
LOWPOWER_CONTROL
16
5
LOWPOWER_AUTO_ENABLE
8
5
INT_ACK
0
4
CTL17
CTL17
0x44
DLL_START_POINT
24
8
DLL_LOCK
16
8
DLL_INCREMENT
8
8
TRC
0
5
CTL18
CTL18
0x48
DLL_DQS_DELAY_1
24
7
DLL_DQS_DELAY_0
16
7
INT_STATUS
8
5
INT_MASK
0
5
CTL19
CTL19
0x4c
DQS_OUT_SHIFT_BYPASS
24
8
DQS_OUT_SHIFT
16
7
DLL_DQS_DELAY_BYPASS_1
8
8
DLL_DQS_DELAY_BYPASS_0
0
8
CTL20
CTL20
0x50
TRCD_INT
24
8
TRAS_MIN
16
8
WR_DQS_SHIFT_BYPASS
8
8
WR_DQS_SHIFT
0
7
CTL21
CTL21
0x54
OUT_OF_RANGE_LENGTH
8
10
TRFC
0
8
CTL22
CTL22
0x58
AHB0_WRCNT
16
11
AHB0_RDCNT
0
11
CTL23
CTL23
0x5c
AHB1_WRCNT
16
11
AHB1_RDCNT
0
11
CTL24
CTL24
0x60
AHB2_WRCNT
16
11
AHB2_RDCNT
0
11
CTL25
CTL25
0x64
AHB3_WRCNT
16
11
AHB3_RDCNT
0
11
CTL26
CTL26
0x68
TREF
0
12
CTL27
CTL27
0x6c
CTL28
CTL28
0x70
CTL29
CTL29
0x74
LOWPOWER_INTERNAL_CNT
16
16
LOWPOWER_EXTERNAL_CNT
0
16
CTL30
CTL30
0x78
LOWPOWER_REFRESH_HOLD
16
16
LOWPOWER_POWER_DOWN_CNT
0
16
CTL31
CTL31
0x7c
TDLL
16
16
LOWPOWER_SELF_REFRESH_CNT
0
16
CTL32
CTL32
0x80
TXSNR
16
16
TRAS_MAX
0
16
CTL33
CTL33
0x84
VERSION
16
16
TXSR
0
16
CTL34
CTL34
0x88
TINIT
0
24
CTL35
CTL35
0x8c
OUT_OF_RANGE_ADDR
0
31
CTL36
CTL36
0x90
PWRUP_SREFRESH_EXIT
24
ENABLE_QUICK_SREFRESH
16
BUS_SHARE_ENABLE
8
ACTIVE_AGING
0
CTL37
CTL37
0x94
BUS_SHARE_TIMEOUT
8
10
TREF_ENABLE
0
CTL38
CTL38
0x98
EMRS2_DATA_0
16
13
EMRS1_DATA
0
13
CTL39
CTL39
0x9c
EMRS2_DATA_2
16
13
EMRS2_DATA_1
0
13
CTL40
CTL40
0xa0
TPDEX
16
16
EMRS2_DATA_3
0
13
DRI
Digital Radio Interface
Digital Radio Interface (DRI)
DRI
0x80074000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
ENABLE_INPUTS
29
ANALOG_LINE_IN
0x0
DRI_DIGITAL_IN
0x1
STOP_ON_OFLOW_ERROR
26
IGNORE
0x0
STOP
0x1
STOP_ON_PILOT_ERROR
25
IGNORE
0x0
STOP
0x1
DMA_DELAY_COUNT
16
5
REACQUIRE_PHASE
15
NORMAL
0x0
NEW_PHASE
0x1
OVERFLOW_IRQ_EN
11
DISABLED
0x0
ENABLED
0x1
PILOT_SYNC_LOSS_IRQ_EN
10
DISABLED
0x0
ENABLED
0x1
ATTENTION_IRQ_EN
9
DISABLED
0x0
ENABLED
0x1
OVERFLOW_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
PILOT_SYNC_LOSS_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
ATTENTION_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
RUN
0
HALT
0x0
RUN
0x1
set
4
clr
8
tog
12
TIMING
TIMING
0x10
PILOT_REP_RATE
16
4
GAP_DETECTION_INTERVAL
0
8
STAT
STAT
0x20
DRI_PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
PILOT_PHASE
16
4
OVERFLOW_IRQ_SUMMARY
3
NO_REQUEST
0x0
REQUEST
0x1
PILOT_SYNC_LOSS_IRQ_SUMMARY
2
NO_REQUEST
0x0
REQUEST
0x1
ATTENTION_IRQ_SUMMARY
1
NO_REQUEST
0x0
REQUEST
0x1
DATA
DATA
0x30
DATA
0
32
DEBUG0
DEBUG0
0x40
DMAREQ
31
DMACMDKICK
30
DRI_CLK_INPUT
29
DRI_DATA_INPUT
28
TEST_MODE
27
PILOT_REP_RATE
26
8_AT_4MHZ
0x0
12_AT_6MHZ
0x1
SPARE
18
8
FRAME
0
18
set
4
clr
8
tog
12
DEBUG1
DEBUG1
0x50
INVERT_PILOT
31
NORMAL
0x0
INVERTED
0x1
INVERT_ATTENTION
30
NORMAL
0x0
INVERTED
0x1
INVERT_DRI_DATA
29
NORMAL
0x0
INVERTED
0x1
INVERT_DRI_CLOCK
28
NORMAL
0x0
INVERTED
0x1
REVERSE_FRAME
27
NORMAL
0x0
REVERSED
0x1
SWIZZLED_FRAME
0
18
set
4
clr
8
tog
12
VERSION
VERSION
0x60
MAJOR
24
8
MINOR
16
8
STEP
0
16
ECC8
Reed-Solomon ECC
8-Symbol Correcting ECC Accelerator (ECC8)
ECC8
0x80008000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
AHBM_SFTRST
29
RUN
0x0
RESET
0x1
THROTTLE
24
4
DEBUG_STALL_IRQ_EN
10
DEBUG_WRITE_IRQ_EN
9
COMPLETE_IRQ_EN
8
BM_ERROR_IRQ
3
DEBUG_STALL_IRQ
2
DEBUG_WRITE_IRQ
1
COMPLETE_IRQ
0
set
4
clr
8
tog
12
STATUS0
STATUS0
0x10
HANDLE
16
16
RS8ECC_ENC_PRESENT
15
RS8ECC_DEC_PRESENT
14
RS4ECC_ENC_PRESENT
13
RS4ECC_DEC_PRESENT
12
STATUS_AUX
8
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
ALLONES
4
CORRECTED
3
UNCORRECTABLE
2
COMPLETED_CE
0
2
STATUS1
STATUS1
0x20
STATUS_PAYLOAD7
28
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD6
24
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD5
20
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD4
16
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD3
12
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD2
8
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD1
4
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
STATUS_PAYLOAD0
0
4
NO_ERRORS
0x0
ONE_CORRECTABLE
0x1
TWO_CORRECTABLE
0x2
THREE_CORRECTABLE
0x3
FOUR_CORRECTABLE
0x4
FIVE_CORRECTABLE
0x5
SIX_CORRECTABLE
0x6
SEVEN_CORRECTABLE
0x7
EIGHT_CORRECTABLE
0x8
NOT_CHECKED
0xc
UNCORRECTABLE
0xe
ALL_ONES
0xf
DEBUG0
DEBUG0
0x30
KES_DEBUG_SYNDROME_SYMBOL
16
9
NORMAL
0x0
TEST_MODE
0x1
KES_DEBUG_SHIFT_SYND
15
KES_DEBUG_PAYLOAD_FLAG
14
DATA
0x1
AUX
0x1
KES_DEBUG_MODE4K
13
4k
0x1
2k
0x1
KES_DEBUG_KICK
12
KES_STANDALONE
11
NORMAL
0x0
TEST_MODE
0x1
KES_DEBUG_STEP
10
KES_DEBUG_STALL
9
NORMAL
0x0
WAIT
0x1
BM_KES_TEST_BYPASS
8
NORMAL
0x0
TEST_MODE
0x1
DEBUG_REG_SELECT
0
6
set
4
clr
8
tog
12
DBGKESREAD
DBGKESREAD
0x40
VALUES
0
32
DBGCSFEREAD
DBGCSFEREAD
0x50
VALUES
0
32
DBGSYNDGENREAD
DBGSYNDGENREAD
0x60
VALUES
0
32
DBGAHBMREAD
DBGAHBMREAD
0x70
VALUES
0
32
BLOCKNAME
BLOCKNAME
0x80
NAME
0
32
VERSION
VERSION
0xa0
MAJOR
24
8
MINOR
16
8
STEP
0
16
EMI
External Memory Interface
External Memory Interface (EMI)
EMI
0x80020000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
MEM_WIDTH
6
WRITE_PROTECT
5
RESET_OUT
4
CE_SELECT
0
4
NONE
0x0
CE0
0x1
CE1
0x2
CE2
0x4
CE3
0x8
set
4
clr
8
tog
12
STAT
STAT
0x10
DRAM_PRESENT
31
NOR_PRESENT
30
LARGE_DRAM_ENABLED
29
DRAM_HALTED
1
NOT_HALTED
0x0
HALTED
0x1
NOR_BUSY
0
NOT_BUSY
0x0
BUSY
0x1
TIME
TIME
0x20
THZ
24
4
TDH
16
4
TDS
8
5
TAS
0
4
set
4
clr
8
tog
12
DDR_TEST_MODE_CSR
DDR_TEST_MODE_CSR
0x30
DONE
1
START
0
set
4
clr
8
tog
12
DEBUG
DEBUG
0x80
NOR_STATE
0
4
DDR_TEST_MODE_STATUS0
DDR_TEST_MODE_STATUS0
0x90
ADDR0
0
13
DDR_TEST_MODE_STATUS1
DDR_TEST_MODE_STATUS1
0xa0
ADDR1
0
13
DDR_TEST_MODE_STATUS2
DDR_TEST_MODE_STATUS2
0xb0
DATA0
0
32
DDR_TEST_MODE_STATUS3
DDR_TEST_MODE_STATUS3
0xc0
DATA1
0
32
VERSION
VERSION
0xf0
MAJOR
24
8
MINOR
16
8
STEP
0
16
GPIOMON
GPIOMON interface
GPIOMON interface
GPIOMON
0x8003c300
BANK0_DATAIN
BANK0_DATAIN
0x0
DATA
0
32
BANK1_DATAIN
BANK1_DATAIN
0x10
DATA
0
32
BANK2_DATAIN
BANK2_DATAIN
0x20
DATA
0
32
BANK3_DATAIN
BANK3_DATAIN
0x30
DATA
0
32
BANK0_DATAOUT
BANK0_DATAOUT
0x40
DATA
0
32
set
4
clr
8
tog
12
BANK1_DATAOUT
BANK1_DATAOUT
0x50
DATA
0
32
set
4
clr
8
tog
12
BANK2_DATAOUT
BANK2_DATAOUT
0x60
DATA
0
32
set
4
clr
8
tog
12
BANK3_DATAOUT
BANK3_DATAOUT
0x70
DATA
0
32
set
4
clr
8
tog
12
BANK0_DATAOEN
BANK0_DATAOEN
0x80
OUTPUT_ENABLES
0
32
set
4
clr
8
tog
12
BANK1_DATAOEN
BANK1_DATAOEN
0x90
OUTPUT_ENABLES
0
32
set
4
clr
8
tog
12
BANK2_DATAOEN
BANK2_DATAOEN
0xa0
OUTPUT_ENABLES
0
32
set
4
clr
8
tog
12
BANK3_DATAOEN
BANK3_DATAOEN
0xb0
OUTPUT_ENABLES
0
32
set
4
clr
8
tog
12
CTRL
CTRL
0xc0
RSRVD
4
28
PINMUX_ALT_RESET
3
OEN_8MA
2
OEN_4MA
1
OEN_NAND
0
set
4
clr
8
tog
12
ALT1_PINMUX_BANK0
ALT1_PINMUX_BANK0
0xd0
INDEX
0
32
set
4
clr
8
tog
12
ALT1_PINMUX_BANK1
ALT1_PINMUX_BANK1
0xe0
INDEX
0
32
set
4
clr
8
tog
12
ALT1_PINMUX_BANK2
ALT1_PINMUX_BANK2
0xf0
INDEX
0
32
set
4
clr
8
tog
12
ALT1_PINMUX_BANK3
ALT1_PINMUX_BANK3
0x100
INDEX
0
32
set
4
clr
8
tog
12
ALT2_PINMUX_BANK0
ALT2_PINMUX_BANK0
0x110
INDEX
0
32
set
4
clr
8
tog
12
ALT2_PINMUX_BANK1
ALT2_PINMUX_BANK1
0x120
INDEX
0
32
set
4
clr
8
tog
12
ALT2_PINMUX_BANK2
ALT2_PINMUX_BANK2
0x130
INDEX
0
32
set
4
clr
8
tog
12
ALT2_PINMUX_BANK3
ALT2_PINMUX_BANK3
0x140
INDEX
0
32
set
4
clr
8
tog
12
ALT3_PINMUX_BANK0
ALT3_PINMUX_BANK0
0x150
INDEX
0
32
set
4
clr
8
tog
12
ALT3_PINMUX_BANK1
ALT3_PINMUX_BANK1
0x160
INDEX
0
32
set
4
clr
8
tog
12
ALT3_PINMUX_BANK2
ALT3_PINMUX_BANK2
0x170
INDEX
0
32
set
4
clr
8
tog
12
ALT3_PINMUX_BANK3
ALT3_PINMUX_BANK3
0x180
INDEX
0
32
set
4
clr
8
tog
12
GPMI
General Purpose Media Interface
General Purpose Media Interface
GPMI
0x8000c000
CTRL0
CTRL0
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
RUN
29
IDLE
0x0
BUSY
0x1
DEV_IRQ_EN
28
TIMEOUT_IRQ_EN
27
UDMA
26
DISABLED
0x0
ENABLED
0x1
COMMAND_MODE
24
2
WRITE
0x0
READ
0x1
READ_AND_COMPARE
0x2
WAIT_FOR_READY
0x3
WORD_LENGTH
23
16_BIT
0x0
8_BIT
0x1
LOCK_CS
22
DISABLED
0x0
ENABLED
0x1
CS
20
2
ADDRESS
17
3
NAND_DATA
0x0
NAND_CLE
0x1
NAND_ALE
0x2
ADDRESS_INCREMENT
16
DISABLED
0x0
ENABLED
0x1
XFER_COUNT
0
16
set
4
clr
8
tog
12
COMPARE
COMPARE
0x10
MASK
16
16
REFERENCE
0
16
ECCCTRL
ECCCTRL
0x20
HANDLE
16
16
ECC_CMD
13
2
DECODE_4_BIT
0x0
ENCODE_4_BIT
0x1
DECODE_8_BIT
0x2
ENCODE_8_BIT
0x3
ENABLE_ECC
12
ENABLE
0x1
DISABLE
0x0
BUFFER_MASK
0
9
AUXILIARY
0x100
BUFFER7
0x80
BUFFER6
0x40
BUFFER5
0x20
BUFFER4
0x10
BUFFER3
0x8
BUFFER2
0x4
BUFFER1
0x2
BUFFER0
0x1
set
4
clr
8
tog
12
ECCCOUNT
ECCCOUNT
0x30
COUNT
0
16
PAYLOAD
PAYLOAD
0x40
ADDRESS
2
30
AUXILIARY
AUXILIARY
0x50
ADDRESS
2
30
CTRL1
CTRL1
0x60
DSAMPLE_TIME
12
3
DMA2ECC_MODE
11
DEV_IRQ
10
TIMEOUT_IRQ
9
BURST_EN
8
ABORT_WAIT_FOR_READY3
7
ABORT_WAIT_FOR_READY2
6
ABORT_WAIT_FOR_READY1
5
ABORT_WAIT_FOR_READY0
4
DEV_RESET
3
ENABLED
0x0
DISABLED
0x1
ATA_IRQRDY_POLARITY
2
ACTIVELOW
0x0
ACTIVEHIGH
0x1
CAMERA_MODE
1
GPMI_MODE
0
NAND
0x0
ATA
0x1
set
4
clr
8
tog
12
TIMING0
TIMING0
0x70
ADDRESS_SETUP
16
8
DATA_HOLD
8
8
DATA_SETUP
0
8
TIMING1
TIMING1
0x80
DEVICE_BUSY_TIMEOUT
16
16
TIMING2
TIMING2
0x90
UDMA_TRP
24
8
UDMA_ENV
16
8
UDMA_HOLD
8
8
UDMA_SETUP
0
8
DATA
DATA
0xa0
DATA
0
32
STAT
STAT
0xb0
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
RDY_TIMEOUT
8
4
ATA_IRQ
7
INVALID_BUFFER_MASK
6
FIFO_EMPTY
5
NOT_EMPTY
0x0
EMPTY
0x1
FIFO_FULL
4
NOT_FULL
0x0
FULL
0x1
DEV3_ERROR
3
DEV2_ERROR
2
DEV1_ERROR
1
DEV0_ERROR
0
DEBUG
DEBUG
0xc0
READY3
31
READY2
30
READY1
29
READY0
28
WAIT_FOR_READY_END3
27
WAIT_FOR_READY_END2
26
WAIT_FOR_READY_END1
25
WAIT_FOR_READY_END0
24
SENSE3
23
SENSE2
22
SENSE1
21
SENSE0
20
DMAREQ3
19
DMAREQ2
18
DMAREQ1
17
DMAREQ0
16
CMD_END
12
4
UDMA_STATE
8
4
BUSY
7
DISABLED
0x0
ENABLED
0x1
PIN_STATE
4
3
PSM_IDLE
0x0
PSM_BYTCNT
0x1
PSM_ADDR
0x2
PSM_STALL
0x3
PSM_STROBE
0x4
PSM_ATARDY
0x5
PSM_DHOLD
0x6
PSM_DONE
0x7
MAIN_STATE
0
4
MSM_IDLE
0x0
MSM_BYTCNT
0x1
MSM_WAITFE
0x2
MSM_WAITFR
0x3
MSM_DMAREQ
0x4
MSM_DMAACK
0x5
MSM_WAITFF
0x6
MSM_LDFIFO
0x7
MSM_LDDMAR
0x8
MSM_RDCMP
0x9
MSM_DONE
0xa
VERSION
VERSION
0xd0
MAJOR
24
8
MINOR
16
8
STEP
0
16
I2C
I2C Interface
I2C Interface
I2C
0x80058000
CTRL0
CTRL0
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
RUN
29
HALT
0x0
RUN
0x1
PRE_ACK
27
ACKNOWLEDGE
26
SNAK
0x0
ACK
0x1
SEND_NAK_ON_LAST
25
ACK_IT
0x0
NAK_IT
0x1
PIO_MODE
24
MULTI_MASTER
23
SINGLE
0x0
MULTIPLE
0x1
CLOCK_HELD
22
RELEASE
0x0
HELD_LOW
0x1
RETAIN_CLOCK
21
RELEASE
0x0
HOLD_LOW
0x1
POST_SEND_STOP
20
NO_STOP
0x0
SEND_STOP
0x1
PRE_SEND_START
19
NO_START
0x0
SEND_START
0x1
SLAVE_ADDRESS_ENABLE
18
DISABLED
0x0
ENABLED
0x1
MASTER_MODE
17
SLAVE
0x0
MASTER
0x1
DIRECTION
16
RECEIVE
0x0
TRANSMIT
0x1
XFER_COUNT
0
16
set
4
clr
8
tog
12
TIMING0
TIMING0
0x10
HIGH_COUNT
16
10
RCV_COUNT
0
10
set
4
clr
8
tog
12
TIMING1
TIMING1
0x20
LOW_COUNT
16
10
XMIT_COUNT
0
10
set
4
clr
8
tog
12
TIMING2
TIMING2
0x30
BUS_FREE
16
10
LEADIN_COUNT
0
10
set
4
clr
8
tog
12
CTRL1
CTRL1
0x40
BCAST_SLAVE_EN
24
NO_BCAST
0x0
WATCH_BCAST
0x1
SLAVE_ADDRESS_BYTE
16
8
BUS_FREE_IRQ_EN
15
DISABLED
0x0
ENABLED
0x1
DATA_ENGINE_CMPLT_IRQ_EN
14
DISABLED
0x0
ENABLED
0x1
NO_SLAVE_ACK_IRQ_EN
13
DISABLED
0x0
ENABLED
0x1
OVERSIZE_XFER_TERM_IRQ_EN
12
DISABLED
0x0
ENABLED
0x1
EARLY_TERM_IRQ_EN
11
DISABLED
0x0
ENABLED
0x1
MASTER_LOSS_IRQ_EN
10
DISABLED
0x0
ENABLED
0x1
SLAVE_STOP_IRQ_EN
9
DISABLED
0x0
ENABLED
0x1
SLAVE_IRQ_EN
8
DISABLED
0x0
ENABLED
0x1
BUS_FREE_IRQ
7
NO_REQUEST
0x0
REQUEST
0x1
DATA_ENGINE_CMPLT_IRQ
6
NO_REQUEST
0x0
REQUEST
0x1
NO_SLAVE_ACK_IRQ
5
NO_REQUEST
0x0
REQUEST
0x1
OVERSIZE_XFER_TERM_IRQ
4
NO_REQUEST
0x0
REQUEST
0x1
EARLY_TERM_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
MASTER_LOSS_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_STOP_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_IRQ
0
NO_REQUEST
0x0
REQUEST
0x1
set
4
clr
8
tog
12
STAT
STAT
0x50
MASTER_PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
SLAVE_PRESENT
30
UNAVAILABLE
0x0
AVAILABLE
0x1
ANY_ENABLED_IRQ
29
NO_REQUESTS
0x0
AT_LEAST_ONE_REQUEST
0x1
RCVD_SLAVE_ADDR
16
8
SLAVE_ADDR_EQ_ZERO
15
ZERO_NOT_MATCHED
0x0
WAS_ZERO
0x1
SLAVE_FOUND
14
IDLE
0x0
WAITING
0x1
SLAVE_SEARCHING
13
IDLE
0x0
ACTIVE
0x1
DATA_ENGINE_DMA_WAIT
12
CONTINUE
0x0
WAITING
0x1
BUS_BUSY
11
IDLE
0x0
BUSY
0x1
CLK_GEN_BUSY
10
IDLE
0x0
BUSY
0x1
DATA_ENGINE_BUSY
9
IDLE
0x0
BUSY
0x1
SLAVE_BUSY
8
IDLE
0x0
BUSY
0x1
BUS_FREE_IRQ_SUMMARY
7
NO_REQUEST
0x0
REQUEST
0x1
DATA_ENGINE_CMPLT_IRQ_SUMMARY
6
NO_REQUEST
0x0
REQUEST
0x1
NO_SLAVE_ACK_IRQ_SUMMARY
5
NO_REQUEST
0x0
REQUEST
0x1
OVERSIZE_XFER_TERM_IRQ_SUMMARY
4
NO_REQUEST
0x0
REQUEST
0x1
EARLY_TERM_IRQ_SUMMARY
3
NO_REQUEST
0x0
REQUEST
0x1
MASTER_LOSS_IRQ_SUMMARY
2
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_STOP_IRQ_SUMMARY
1
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_IRQ_SUMMARY
0
NO_REQUEST
0x0
REQUEST
0x1
DATA
DATA
0x60
DATA
0
32
DEBUG0
DEBUG0
0x70
DMAREQ
31
DMAENDCMD
30
DMAKICK
29
TBD
26
3
DMA_STATE
16
10
START_TOGGLE
15
STOP_TOGGLE
14
GRAB_TOGGLE
13
CHANGE_TOGGLE
12
TESTMODE
11
SLAVE_HOLD_CLK
10
SLAVE_STATE
0
10
set
4
clr
8
tog
12
DEBUG1
DEBUG1
0x80
I2C_CLK_IN
31
I2C_DATA_IN
30
DMA_BYTE_ENABLES
24
4
CLK_GEN_STATE
16
7
LST_MODE
9
2
BCAST
0x0
MY_WRITE
0x1
MY_READ
0x2
NOT_ME
0x3
LOCAL_SLAVE_TEST
8
FORCE_CLK_ON
5
FORCE_CLK_IDLE
4
FORCE_ARB_LOSS
3
FORCE_RCV_ACK
2
FORCE_I2C_DATA_OE
1
FORCE_I2C_CLK_OE
0
set
4
clr
8
tog
12
VERSION
VERSION
0x90
MAJOR
24
8
MINOR
16
8
STEP
0
16
ICOLL
Interrupt Collector
Interrupt Collector
ICOLL
0x80000000
VECTOR
VECTOR
0x0
IRQVECTOR
2
30
set
4
clr
8
tog
12
LEVELACK
LEVELACK
0x10
IRQLEVELACK
0
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
CTRL
CTRL
0x20
SFTRST
31
RUN
0x0
IN_RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLOCKS
0x1
VECTOR_PITCH
21
3
DEFAULT_BY4
0x0
BY4
0x1
BY8
0x2
BY12
0x3
BY16
0x4
BY20
0x5
BY24
0x6
BY28
0x7
BYPASS_FSM
20
NORMAL
0x0
BYPASS
0x1
NO_NESTING
19
NORMAL
0x0
NO_NEST
0x1
ARM_RSE_MODE
18
MUST_WRITE
0x0
READ_SIDE_EFFECT
0x1
FIQ_FINAL_ENABLE
17
DISABLE
0x0
ENABLE
0x1
IRQ_FINAL_ENABLE
16
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ35
7
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ34
6
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ33
5
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ32
4
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ_T3
3
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ_T2
2
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ_T1
1
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ_T0
0
DISABLE
0x0
ENABLE
0x1
set
4
clr
8
tog
12
STAT
STAT
0x30
VECTOR_NUMBER
0
6
RAWn
RAWn
0
2
0x40
0x10
RAW_IRQS
0
32
PRIORITYn
PRIORITYn
0
16
0x60
0x10
SOFTIRQ3
27
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE3
26
DISABLE
0x0
ENABLE
0x1
PRIORITY3
24
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ2
19
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE2
18
DISABLE
0x0
ENABLE
0x1
PRIORITY2
16
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ1
11
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE1
10
DISABLE
0x0
ENABLE
0x1
PRIORITY1
8
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ0
3
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE0
2
DISABLE
0x0
ENABLE
0x1
PRIORITY0
0
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
set
4
clr
8
tog
12
VBASE
VBASE
0x160
TABLE_ADDRESS
2
30
set
4
clr
8
tog
12
DEBUG
DEBUG
0x170
INSERVICE
28
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
LEVEL_REQUESTS
24
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
REQUESTS_BY_LEVEL
20
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
FIQ
17
NO_FIQ_REQUESTED
0x0
FIQ_REQUESTED
0x1
IRQ
16
NO_IRQ_REQUESTED
0x0
IRQ_REQUESTED
0x1
VECTOR_FSM
0
10
FSM_IDLE
0x0
FSM_MULTICYCLE1
0x1
FSM_MULTICYCLE2
0x2
FSM_PENDING
0x4
FSM_MULTICYCLE3
0x8
FSM_MULTICYCLE4
0x10
FSM_ISR_RUNNING1
0x20
FSM_ISR_RUNNING2
0x40
FSM_ISR_RUNNING3
0x80
FSM_MULTICYCLE5
0x100
FSM_MULTICYCLE6
0x200
DBGREAD0
DBGREAD0
0x180
VALUE
0
32
DBGREAD1
DBGREAD1
0x190
VALUE
0
32
DBGFLAG
DBGFLAG
0x1a0
FLAG
0
16
set
4
clr
8
tog
12
DBGREQUESTn
DBGREQUESTn
0
2
0x1b0
0x10
BITS
0
32
VERSION
VERSION
0x1d0
MAJOR
24
8
MINOR
16
8
STEP
0
16
IR
IrDA
IrDA Controller
IR
0x80078000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
MTA
24
3
MTA_10MS
0x0
MTA_5MS
0x1
MTA_1MS
0x2
MTA_500US
0x3
MTA_100US
0x4
MTA_50US
0x5
MTA_10US
0x6
MTA_0
0x7
MODE
22
2
SIR
0x0
MIR
0x1
FIR
0x2
VFIR
0x3
SPEED
19
3
SPD000
0x0
SPD001
0x1
SPD010
0x2
SPD011
0x3
SPD100
0x4
SPD101
0x5
TC_TIME_DIV
8
6
TC_TYPE
7
SIR_GAP
4
3
GAP_10K
0x0
GAP_5K
0x1
GAP_1K
0x2
GAP_500
0x3
GAP_100
0x4
GAP_50
0x5
GAP_10
0x6
GAP_0
0x7
SIPEN
3
TCEN
2
TXEN
1
RXEN
0
set
4
clr
8
tog
12
TXDMA
TXDMA
0x10
RUN
31
EMPTY
29
INT
28
CHANGE
27
NEW_MTA
24
3
NEW_MODE
22
2
NEW_SPEED
19
3
BOF_TYPE
18
XBOFS
12
6
XFER_COUNT
0
12
set
4
clr
8
tog
12
RXDMA
RXDMA
0x20
RUN
31
XFER_COUNT
0
10
set
4
clr
8
tog
12
DBGCTRL
DBGCTRL
0x30
VFIRSWZ
12
NORMAL
0x0
SWAP
0x1
RXFRMOFF
11
RXCRCOFF
10
RXINVERT
9
TXFRMOFF
8
TXCRCOFF
7
TXINVERT
6
INTLOOPBACK
5
DUPLEX
4
MIO_RX
3
MIO_TX
2
MIO_SCLK
1
MIO_EN
0
set
4
clr
8
tog
12
INTR
INTR
0x40
RXABORT_IRQ_EN
22
DISABLED
0x0
ENABLED
0x1
SPEED_IRQ_EN
21
DISABLED
0x0
ENABLED
0x1
RXOF_IRQ_EN
20
DISABLED
0x0
ENABLED
0x1
TXUF_IRQ_EN
19
DISABLED
0x0
ENABLED
0x1
TC_IRQ_EN
18
DISABLED
0x0
ENABLED
0x1
RX_IRQ_EN
17
DISABLED
0x0
ENABLED
0x1
TX_IRQ_EN
16
DISABLED
0x0
ENABLED
0x1
RXABORT_IRQ
6
NO_REQUEST
0x0
REQUEST
0x1
SPEED_IRQ
5
NO_REQUEST
0x0
REQUEST
0x1
RXOF_IRQ
4
NO_REQUEST
0x0
REQUEST
0x1
TXUF_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
TC_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
RX_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
TX_IRQ
0
NO_REQUEST
0x0
REQUEST
0x1
set
4
clr
8
tog
12
DATA
DATA
0x50
DATA
0
32
STAT
STAT
0x60
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
MODE_ALLOWED
29
2
VFIR
0x0
FIR
0x1
MIR
0x2
SIR
0x3
ANY_IRQ
28
NO_REQUEST
0x0
REQUEST
0x1
RXABORT_SUMMARY
22
NO_REQUEST
0x0
REQUEST
0x1
SPEED_SUMMARY
21
NO_REQUEST
0x0
REQUEST
0x1
RXOF_SUMMARY
20
NO_REQUEST
0x0
REQUEST
0x1
TXUF_SUMMARY
19
NO_REQUEST
0x0
REQUEST
0x1
TC_SUMMARY
18
NO_REQUEST
0x0
REQUEST
0x1
RX_SUMMARY
17
NO_REQUEST
0x0
REQUEST
0x1
TX_SUMMARY
16
NO_REQUEST
0x0
REQUEST
0x1
MEDIA_BUSY
2
RX_ACTIVE
1
TX_ACTIVE
0
TCCTRL
TCCTRL
0x70
INIT
31
GO
30
BUSY
29
TEMIC
24
LOW
0x0
HIGH
0x1
EXT_DATA
16
8
DATA
8
8
ADDR
5
3
INDX
1
4
C
0
set
4
clr
8
tog
12
SI_READ
SI_READ
0x80
ABORT
8
DATA
0
8
DEBUG
DEBUG
0x90
TXDMAKICK
5
RXDMAKICK
4
TXDMAEND
3
RXDMAEND
2
TXDMAREQ
1
RXDMAREQ
0
VERSION
VERSION
0xa0
MAJOR
24
8
MINOR
16
8
STEP
0
16
LCDIF
LCD Interface
LCD Interface (LCDIF)
LCDIF
0x80030000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
READ_WRITEB
29
WAIT_FOR_VSYNC_EDGE
28
DATA_SHIFT_DIR
27
TXDATA_SHIFT_LEFT
0x0
TXDATA_SHIFT_RIGHT
0x1
SHIFT_NUM_BITS
25
2
DVI_MODE
24
BYPASS_COUNT
23
DATA_SWIZZLE
21
2
NO_SWAP
0x0
LITTLE_ENDIAN
0x0
BIG_ENDIAN_SWAP
0x1
SWAP_ALL_BYTES
0x1
HWD_SWAP
0x2
HWD_BYTE_SWAP
0x3
VSYNC_MODE
20
DOTCLK_MODE
19
DATA_SELECT
18
CMD_MODE
0x0
DATA_MODE
0x1
WORD_LENGTH
17
16_BIT
0x0
8_BIT
0x1
RUN
16
COUNT
0
16
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
BYTE_PACKING_FORMAT
16
4
OVERFLOW_IRQ_EN
15
UNDERFLOW_IRQ_EN
14
CUR_FRAME_DONE_IRQ_EN
13
VSYNC_EDGE_IRQ_EN
12
OVERFLOW_IRQ
11
NO_REQUEST
0x0
REQUEST
0x1
UNDERFLOW_IRQ
10
NO_REQUEST
0x0
REQUEST
0x1
CUR_FRAME_DONE_IRQ
9
NO_REQUEST
0x0
REQUEST
0x1
VSYNC_EDGE_IRQ
8
NO_REQUEST
0x0
REQUEST
0x1
READ_MODE_NUM_PACKED_SUBWORDS
5
3
FIRST_READ_DUMMY
4
LCD_CS_CTRL
3
BUSY_ENABLE
2
BUSY_DISABLED
0x0
BUSY_ENABLED
0x1
MODE86
1
8080_MODE
0x0
6800_MODE
0x1
RESET
0
LCDRESET_LOW
0x0
LCDRESET_HIGH
0x1
set
4
clr
8
tog
12
TIMING
TIMING
0x20
CMD_HOLD
24
8
CMD_SETUP
16
8
DATA_HOLD
8
8
DATA_SETUP
0
8
VDCTRL0
VDCTRL0
0x30
VSYNC_OEB
29
VSYNC_OUTPUT
0x0
VSYNC_INPUT
0x1
ENABLE_PRESENT
28
VSYNC_POL
27
HSYNC_POL
26
DOTCLK_POL
25
ENABLE_POL
24
VSYNC_PERIOD_UNIT
21
VSYNC_PULSE_WIDTH_UNIT
20
INTERLACE
19
DOTCLK_V_VALID_DATA_CNT
0
10
set
4
clr
8
tog
12
VDCTRL1
VDCTRL1
0x40
VSYNC_PULSE_WIDTH
20
12
VSYNC_PERIOD
0
20
VDCTRL2
VDCTRL2
0x50
HSYNC_PULSE_WIDTH
23
9
HSYNC_PERIOD
11
12
DOTCLK_H_VALID_DATA_CNT
0
11
VDCTRL3
VDCTRL3
0x60
SYNC_SIGNALS_ON
24
HORIZONTAL_WAIT_CNT
12
12
VERTICAL_WAIT_CNT
0
9
DVICTRL0
DVICTRL0
0x70
H_ACTIVE_CNT
20
11
H_BLANKING_CNT
10
10
V_LINES_CNT
0
10
DVICTRL1
DVICTRL1
0x80
F1_START_LINE
20
10
F1_END_LINE
10
10
F2_START_LINE
0
10
DVICTRL2
DVICTRL2
0x90
F2_END_LINE
20
10
V1_BLANK_START_LINE
10
10
V1_BLANK_END_LINE
0
10
DVICTRL3
DVICTRL3
0xa0
V2_BLANK_START_LINE
16
10
V2_BLANK_END_LINE
0
10
DATA
DATA
0xb0
DATA_THREE
24
8
DATA_TWO
16
8
DATA_ONE
8
8
DATA_ZERO
0
8
STAT
STAT
0xc0
PRESENT
31
DMA_REQ
30
RXFIFO_FULL
29
RXFIFO_EMPTY
28
TXFIFO_FULL
27
TXFIFO_EMPTY
26
BUSY
25
DVI_CURRENT_FIELD
24
VERSION
VERSION
0xd0
MAJOR
24
8
MINOR
16
8
STEP
0
16
DEBUG0
DEBUG0
0xe0
STREAMING_END_DETECTED
31
WAIT_FOR_VSYNC_EDGE_OUT
30
SYNC_SIGNALS_ON_REG
29
DMACMDKICK
28
ENABLE
27
HSYNC
26
VSYNC
25
CUR_FRAME_TX
24
EMPTY_WORD
23
CUR_STATE
16
7
DATA_COUNT
0
16
LRADC
Low Resolution ADC
Low-Resolution ADC and Touch-Screen Interface
LRADC
0x80050000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
ONCHIP_GROUNDREF
21
OFF
0x0
ON
0x1
TOUCH_DETECT_ENABLE
20
OFF
0x0
ON
0x1
YMINUS_ENABLE
19
OFF
0x0
ON
0x1
XMINUS_ENABLE
18
OFF
0x0
ON
0x1
YPLUS_ENABLE
17
OFF
0x0
ON
0x1
XPLUS_ENABLE
16
OFF
0x0
ON
0x1
SCHEDULE
0
8
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
TOUCH_DETECT_IRQ_EN
24
DISABLE
0x0
ENABLE
0x1
LRADC7_IRQ_EN
23
DISABLE
0x0
ENABLE
0x1
LRADC6_IRQ_EN
22
DISABLE
0x0
ENABLE
0x1
LRADC5_IRQ_EN
21
DISABLE
0x0
ENABLE
0x1
LRADC4_IRQ_EN
20
DISABLE
0x0
ENABLE
0x1
LRADC3_IRQ_EN
19
DISABLE
0x0
ENABLE
0x1
LRADC2_IRQ_EN
18
DISABLE
0x0
ENABLE
0x1
LRADC1_IRQ_EN
17
DISABLE
0x0
ENABLE
0x1
LRADC0_IRQ_EN
16
DISABLE
0x0
ENABLE
0x1
TOUCH_DETECT_IRQ
8
CLEAR
0x0
PENDING
0x1
LRADC7_IRQ
7
CLEAR
0x0
PENDING
0x1
LRADC6_IRQ
6
CLEAR
0x0
PENDING
0x1
LRADC5_IRQ
5
CLEAR
0x0
PENDING
0x1
LRADC4_IRQ
4
CLEAR
0x0
PENDING
0x1
LRADC3_IRQ
3
CLEAR
0x0
PENDING
0x1
LRADC2_IRQ
2
CLEAR
0x0
PENDING
0x1
LRADC1_IRQ
1
CLEAR
0x0
PENDING
0x1
LRADC0_IRQ
0
CLEAR
0x0
PENDING
0x1
set
4
clr
8
tog
12
CTRL2
CTRL2
0x20
DIVIDE_BY_TWO
24
8
BL_AMP_BYPASS
23
DISABLE
0x0
ENABLE
0x1
BL_ENABLE
22
BL_MUX_SELECT
21
BL_BRIGHTNESS
16
5
TEMPSENSE_PWD
15
DISABLE
0x0
ENABLE
0x1
EXT_EN1
13
DISABLE
0x0
ENABLE
0x1
EXT_EN0
12
TEMP_SENSOR_IENABLE1
9
DISABLE
0x0
ENABLE
0x1
TEMP_SENSOR_IENABLE0
8
DISABLE
0x0
ENABLE
0x1
TEMP_ISRC1
4
4
300
0xf
280
0xe
260
0xd
240
0xc
220
0xb
200
0xa
180
0x9
160
0x8
140
0x7
120
0x6
100
0x5
80
0x4
60
0x3
40
0x2
20
0x1
ZERO
0x0
TEMP_ISRC0
0
4
300
0xf
280
0xe
260
0xd
240
0xc
220
0xb
200
0xa
180
0x9
160
0x8
140
0x7
120
0x6
100
0x5
80
0x4
60
0x3
40
0x2
20
0x1
ZERO
0x0
set
4
clr
8
tog
12
CTRL3
CTRL3
0x30
DISCARD
24
2
1_SAMPLE
0x1
2_SAMPLES
0x2
3_SAMPLES
0x3
FORCE_ANALOG_PWUP
23
OFF
0x0
ON
0x1
FORCE_ANALOG_PWDN
22
ON
0x0
OFF
0x1
CYCLE_TIME
8
2
6MHZ
0x0
4MHZ
0x1
3MHZ
0x2
2MHZ
0x3
HIGH_TIME
4
2
42NS
0x0
83NS
0x1
125NS
0x2
250NS
0x3
DELAY_CLOCK
1
NORMAL
0x0
DELAYED
0x1
INVERT_CLOCK
0
NORMAL
0x0
INVERT
0x1
set
4
clr
8
tog
12
STATUS
STATUS
0x40
TEMP1_PRESENT
26
TEMP0_PRESENT
25
TOUCH_PANEL_PRESENT
24
CHANNEL7_PRESENT
23
CHANNEL6_PRESENT
22
CHANNEL5_PRESENT
21
CHANNEL4_PRESENT
20
CHANNEL3_PRESENT
19
CHANNEL2_PRESENT
18
CHANNEL1_PRESENT
17
CHANNEL0_PRESENT
16
TOUCH_DETECT_RAW
0
OPEN
0x0
HIT
0x1
CHn
CHn
0
8
0x50
0x10
TOGGLE
31
ACCUMULATE
29
NUM_SAMPLES
24
5
VALUE
0
18
set
4
clr
8
tog
12
DELAYn
DELAYn
0
4
0xd0
0x10
TRIGGER_LRADCS
24
8
KICK
20
TRIGGER_DELAYS
16
4
LOOP_COUNT
11
5
DELAY
0
11
set
4
clr
8
tog
12
DEBUG0
DEBUG0
0x110
READONLY
16
16
STATE
0
12
DEBUG1
DEBUG1
0x120
REQUEST
16
8
TESTMODE_COUNT
8
5
TESTMODE6
2
NORMAL
0x0
TEST
0x1
TESTMODE5
1
NORMAL
0x0
TEST
0x1
TESTMODE
0
NORMAL
0x0
TEST
0x1
set
4
clr
8
tog
12
CONVERSION
CONVERSION
0x130
AUTOMATIC
20
DISABLE
0x0
ENABLE
0x1
SCALE_FACTOR
16
2
NIMH
0x0
DUAL_NIMH
0x1
LI_ION
0x2
ALT_LI_ION
0x3
SCALED_BATT_VOLTAGE
0
10
set
4
clr
8
tog
12
CTRL4
CTRL4
0x140
LRADC7SELECT
28
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC6SELECT
24
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC5SELECT
20
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC4SELECT
16
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC3SELECT
12
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC2SELECT
8
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC1SELECT
4
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC0SELECT
0
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
set
4
clr
8
tog
12
VERSION
VERSION
0x150
MAJOR
24
8
MINOR
16
8
STEP
0
16
OCOTP
One-time Programmable Array Controller
On-Chip OTP (OCOTP) Controller
OCOTP
0x8002c000
CTRL
CTRL
0x0
WR_UNLOCK
16
16
KEY
0x3e77
RELOAD_SHADOWS
13
RD_BANK_OPEN
12
ERROR
9
BUSY
8
ADDR
0
5
set
4
clr
8
tog
12
DATA
DATA
0x10
DATA
0
32
CUSTn
CUSTn
0
4
0x20
0x10
BITS
0
32
CRYPTOn
CRYPTOn
0
4
0x60
0x10
BITS
0
32
HWCAPn
HWCAPn
0
6
0xa0
0x10
BITS
0
32
SWCAP
SWCAP
0x100
BITS
0
32
CUSTCAP
CUSTCAP
0x110
BITS
0
32
LOCK
LOCK
0x120
ROM7
31
ROM6
30
ROM5
29
ROM4
28
ROM3
27
ROM2
26
ROM1
25
ROM0
24
HWSW_SHADOW_ALT
23
CRYPTODCP_ALT
22
CRYPTOKEY_ALT
21
PIN
20
OPS
19
UN2
18
UN1
17
UN0
16
UNALLOCATED
10
6
CUSTCAP
9
HWSW
8
CUSTCAP_SHADOW
7
HWSW_SHADOW
6
CRYPTODCP
5
CRYPTOKEY
4
CUST3
3
CUST2
2
CUST1
1
CUST0
0
OPSn
OPSn
0
4
0x130
0x10
BITS
0
32
UNn
UNn
0
3
0x170
0x10
BITS
0
32
ROMn
ROMn
0
8
0x1a0
0x10
BITS
0
32
VERSION
VERSION
0x220
MAJOR
24
8
MINOR
16
8
STEP
0
16
PINCTRL
Pin Control
Pin Control and GPIO
PINCTRL
0x80018000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PRESENT3
29
PRESENT2
28
PRESENT1
27
PRESENT0
26
IRQOUT3
3
IRQOUT2
2
IRQOUT1
1
IRQOUT0
0
set
4
clr
8
tog
12
MUXSELn
MUXSELn
0
8
0x100
0x10
BITS
0
32
set
4
clr
8
tog
12
DRIVEn
DRIVEn
0
15
0x200
0x10
BITS
0
32
set
4
clr
8
tog
12
PULLn
PULLn
0
4
0x300
0x10
BITS
0
32
set
4
clr
8
tog
12
DOUTn
DOUTn
0
3
0x400
0x10
BITS
0
32
set
4
clr
8
tog
12
DINn
DINn
0
3
0x500
0x10
BITS
0
32
set
4
clr
8
tog
12
DOEn
DOEn
0
3
0x600
0x10
BITS
0
32
set
4
clr
8
tog
12
PIN2IRQn
PIN2IRQn
0
3
0x700
0x10
BITS
0
32
set
4
clr
8
tog
12
IRQENn
IRQENn
0
3
0x800
0x10
BITS
0
32
set
4
clr
8
tog
12
IRQLEVELn
IRQLEVELn
0
3
0x900
0x10
BITS
0
32
set
4
clr
8
tog
12
IRQPOLn
IRQPOLn
0
3
0xa00
0x10
BITS
0
32
set
4
clr
8
tog
12
IRQSTATn
IRQSTATn
0
3
0xb00
0x10
BITS
0
32
set
4
clr
8
tog
12
POWER
Power Control
Power Supply
POWER
0x80044000
CTRL
CTRL
0x0
CLKGATE
30
PSWITCH_IRQ
22
PSWITCH_IRQ_SRC
21
POLARITY_PSWITCH
20
ENIRQ_PSWITCH
19
POLARITY_LINREG_OK
18
LINREG_OK_IRQ
17
ENIRQ_LINREG_OK
16
DC_OK_IRQ
15
ENIRQ_DC_OK
14
BATT_BO_IRQ
13
ENIRQBATT_BO
12
VDDIO_BO_IRQ
11
ENIRQ_VDDIO_BO
10
VDDA_BO_IRQ
9
ENIRQ_VDDA_BO
8
VDDD_BO_IRQ
7
ENIRQ_VDDD_BO
6
POLARITY_VBUSVALID
5
VBUSVALID_IRQ
4
ENIRQ_VBUS_VALID
3
POLARITY_VDD5V_GT_VDDIO
2
VDD5V_GT_VDDIO_IRQ
1
ENIRQ_VDD5V_GT_VDDIO
0
set
4
clr
8
tog
12
5VCTRL
5VCTRL
0x10
VBUSVALID_TRSH
10
2
PWDN_5VBRNOUT
8
ENABLE_ILIMIT
7
DCDC_XFER
6
EN_BATT_PULLDN
5
VBUSVALID_5VDETECT
4
VBUSVALID_TO_B
3
ILIMIT_EQ_ZERO
2
OTG_PWRUP_CMPS
1
ENABLE_DCDC
0
set
4
clr
8
tog
12
MINPWR
MINPWR
0x20
PWD_BO
11
USB_I_SUSPEND
10
ENABLE_OSC
9
SELECT_OSC
8
VBG_OFF
7
DOUBLE_FETS
6
HALF_FETS
5
LESSANA_I
4
PWD_XTAL24
3
DC_STOPCLK
2
EN_DC_PFM
1
DC_HALFCLK
0
set
4
clr
8
tog
12
CHARGE
CHARGE
0x30
ENABLE_FAULT_DETECT
20
CHRG_STS_OFF
19
USE_EXTERN_R
17
PWD_BATTCHRG
16
STOP_ILIMIT
8
4
BATTCHRG_I
0
6
set
4
clr
8
tog
12
VDDDCTRL
VDDDCTRL
0x40
ADJTN
28
4
ALKALINE_CHARGE
24
DISABLE_STEPPING
23
LINREG_FROM_BATT
22
ENABLE_LINREG
21
DISABLE_FET
20
LINREG_OFFSET
16
2
BO_OFFSET
8
3
TRG
0
5
VDDACTRL
VDDACTRL
0x50
DISABLE_STEPPING
18
ENABLE_LINREG
17
DISABLE_FET
16
LINREG_OFFSET
12
2
BO_OFFSET
8
3
TRG
0
5
VDDIOCTRL
VDDIOCTRL
0x60
ADJTN
16
4
DISABLE_STEPPING
15
DISABLE_FET
14
LINREG_OFFSET
12
2
BO_OFFSET
8
3
TRG
0
5
DCFUNCV
DCFUNCV
0x70
VDDD
16
10
VDDIO
0
10
MISC
MISC
0x80
FREQSEL
4
2
DELAY_TIMING
3
TEST
2
SEL_PLLCLK
1
PERIPHERALSWOFF
0
DCLIMITS
DCLIMITS
0x90
POSLIMIT_BOOST
16
7
POSLIMIT_BUCK
8
7
NEGLIMIT
0
7
LOOPCTRL
LOOPCTRL
0xa0
TOGGLE_DIF
20
HYST_SIGN
19
EN_CM_HYST
18
EN_DF_HYST
17
CM_HYST_THRESH
16
DF_HYST_THRESH
15
RCSCALE_THRESH
14
EN_RCSCALE
12
2
DC_FF
8
3
DC_R
4
4
DC_C
0
2
set
4
clr
8
tog
12
STS
STS
0xb0
BATT_CHRG_PRESENT
31
PSWITCH
18
2
AVALID_STATUS
17
BVALID_STATUS
16
VBUSVALID_STATUS
15
SESSEND_STATUS
14
MODE
13
BATT_BO
12
VDD5V_FAULT
11
CHRGSTS
10
LINREG_OK
9
DC_OK
8
VDDIO_BO
7
VDDA_BO
6
VDDD_BO
5
VDD5V_GT_VDDIO
4
AVALID
3
BVALID
2
VBUSVALID
1
SESSEND
0
SPEED
SPEED
0xc0
STATUS
16
8
CTRL
0
2
set
4
clr
8
tog
12
BATTMONITOR
BATTMONITOR
0xd0
BATT_VAL
16
10
EN_BATADJ
6
PWDN_BATTBRNOUT
5
BRWNOUT_PWD
4
BRWNOUT_LVL
0
4
RESET
RESET
0xe0
UNLOCK
16
16
KEY
0x3e77
PWD_OFF
1
PWD
0
set
4
clr
8
tog
12
DEBUG
DEBUG
0xf0
VBUSVALIDPIOLOCK
3
AVALIDPIOLOCK
2
BVALIDPIOLOCK
1
SESSENDPIOLOCK
0
set
4
clr
8
tog
12
SPECIAL
SPECIAL
0x100
TEST
0
32
set
4
clr
8
tog
12
VERSION
VERSION
0x110
MAJOR
24
8
MINOR
16
8
STEP
0
16
PWM
Pulse width Modulation
Pulse-Width Modulator (PWM) Controller
PWM
0x80064000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PWM4_PRESENT
29
PWM3_PRESENT
28
PWM2_PRESENT
27
PWM1_PRESENT
26
PWM0_PRESENT
25
PWM2_ANA_CTRL_ENABLE
5
PWM4_ENABLE
4
PWM3_ENABLE
3
PWM2_ENABLE
2
PWM1_ENABLE
1
PWM0_ENABLE
0
set
4
clr
8
tog
12
ACTIVEn
ACTIVEn
0
5
0x10
0x20
INACTIVE
16
16
ACTIVE
0
16
set
4
clr
8
tog
12
PERIODn
PERIODn
0
5
0x20
0x20
MATT
23
CDIV
20
3
DIV_1
0x0
DIV_2
0x1
DIV_4
0x2
DIV_8
0x3
DIV_16
0x4
DIV_64
0x5
DIV_256
0x6
DIV_1024
0x7
INACTIVE_STATE
18
2
HI_Z
0x0
0
0x2
1
0x3
ACTIVE_STATE
16
2
HI_Z
0x0
0
0x2
1
0x3
PERIOD
0
16
set
4
clr
8
tog
12
VERSION
VERSION
0xb0
MAJOR
24
8
MINOR
16
8
STEP
0
16
RTC
Real Time Clock
Real-Time Clock, Alarm, Watchdog, Persistent Bits
RTC
0x8005c000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
SUPPRESS_COPY2ANALOG
6
FORCE_UPDATE
5
WATCHDOGEN
4
ONEMSEC_IRQ
3
ALARM_IRQ
2
ONEMSEC_IRQ_EN
1
ALARM_IRQ_EN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
RTC_PRESENT
31
ALARM_PRESENT
30
WATCHDOG_PRESENT
29
XTAL32000_PRESENT
28
XTAL32768_PRESENT
27
STALE_REGS
16
8
NEW_REGS
8
8
MILLISECONDS
MILLISECONDS
0x20
COUNT
0
32
set
4
clr
8
tog
12
SECONDS
SECONDS
0x30
COUNT
0
32
set
4
clr
8
tog
12
ALARM
ALARM
0x40
VALUE
0
32
set
4
clr
8
tog
12
WATCHDOG
WATCHDOG
0x50
COUNT
0
32
set
4
clr
8
tog
12
PERSISTENT0
PERSISTENT0
0x60
SPARE_ANALOG
18
14
AUTO_RESTART
17
DISABLE_PSWITCH
16
LOWERBIAS
14
2
DISABLE_XTALOK
13
MSEC_RES
8
5
ALARM_WAKE
7
XTAL32_FREQ
6
XTAL32KHZ_PWRUP
5
XTAL24MHZ_PWRUP
4
LCK_SECS
3
ALARM_EN
2
ALARM_WAKE_EN
1
CLOCKSOURCE
0
set
4
clr
8
tog
12
PERSISTENT1
PERSISTENT1
0x70
GENERAL
0
32
SPARE3
0x4000
SDRAM_BOOT
0x2000
ENUMERATE_500MA_TWICE
0x1000
USB_BOOT_PLAYER_MODE
0x800
SKIP_CHECKDISK
0x400
USB_LOW_POWER_MODE
0x200
OTG_HNP_BIT
0x100
OTG_ATL_ROLE_BIT
0x80
SDRAM_CS_HI
0x40
SDRAM_CS_LO
0x20
SDRAM_NDX_3
0x10
SDRAM_NDX_2
0x8
SDRAM_NDX_1
0x4
SDRAM_NDX_0
0x2
ETM_ENABLE
0x1
set
4
clr
8
tog
12
PERSISTENT2
PERSISTENT2
0x80
GENERAL
0
32
set
4
clr
8
tog
12
PERSISTENT3
PERSISTENT3
0x90
GENERAL
0
32
set
4
clr
8
tog
12
PERSISTENT4
PERSISTENT4
0xa0
GENERAL
0
32
set
4
clr
8
tog
12
PERSISTENT5
PERSISTENT5
0xb0
GENERAL
0
32
set
4
clr
8
tog
12
DEBUG
DEBUG
0xc0
WATCHDOG_RESET_MASK
1
WATCHDOG_RESET
0
set
4
clr
8
tog
12
VERSION
VERSION
0xd0
MAJOR
24
8
MINOR
16
8
STEP
0
16
SAIF
Sync Audio Interface
Sync Audio Interface (SAIF)
SAIF
1
0x80042000
0x80046000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
BITCLK_MULT_RATE
27
3
BITCLK_BASE_RATE
26
FIFO_ERROR_IRQ_EN
25
FIFO_SERVICE_IRQ_EN
24
DMAWAIT_COUNT
16
5
CHANNEL_NUM_SELECT
14
2
BIT_ORDER
12
DELAY
11
JUSTIFY
10
LRCLK_POLARITY
9
BITCLK_EDGE
8
WORD_LENGTH
4
4
BITCLK_48XFS_ENABLE
3
SLAVE_MODE
2
READ_MODE
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
PRESENT
31
DMA_PREQ
16
FIFO_UNDERFLOW_IRQ
6
FIFO_OVERFLOW_IRQ
5
FIFO_SERVICE_IRQ
4
BUSY
0
set
4
clr
8
tog
12
DATA
DATA
0x20
PCM_RIGHT
16
16
PCM_LEFT
0
16
set
4
clr
8
tog
12
VERSION
VERSION
0x30
MAJOR
24
8
MINOR
16
8
STEP
0
16
SPDIF
Sony/Phillips Digital Audio Interface
SPDIF Transmitter
SPDIF
0x80054000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
WAIT_END_XFER
5
WORD_LENGTH
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
PRESENT
31
END_XFER
0
FRAMECTRL
FRAMECTRL
0x20
V_CONFIG
17
AUTO_MUTE
16
USER_DATA
14
V
13
L
12
CC
4
7
PRE
3
COPY
2
AUDIO
1
PRO
0
set
4
clr
8
tog
12
SRR
SRR
0x30
BASEMULT
28
3
RATE
0
20
set
4
clr
8
tog
12
DEBUG
DEBUG
0x40
DMA_PREQ
1
FIFO_STATUS
0
DATA
DATA
0x50
HIGH
16
16
LOW
0
16
set
4
clr
8
tog
12
VERSION
VERSION
0x60
MAJOR
24
8
MINOR
16
8
STEP
0
16
SSP
Sync Serial Port
Synchronous Serial Ports (SSP)
SSP
1
0x80010000
0x80034000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RUN
29
SDIO_IRQ_CHECK
28
LOCK_CS
27
IGNORE_CRC
26
READ
25
DATA_XFER
24
BUS_WIDTH
22
2
ONE_BIT
0x0
FOUR_BIT
0x1
EIGHT_BIT
0x2
WAIT_FOR_IRQ
21
WAIT_FOR_CMD
20
LONG_RESP
19
CHECK_RESP
18
GET_RESP
17
ENABLE
16
XFER_COUNT
0
16
set
4
clr
8
tog
12
CMD0
CMD0
0x10
APPEND_8CYC
20
BLOCK_SIZE
16
4
BLOCK_COUNT
8
8
CMD
0
8
MMC_GO_IDLE_STATE
0x0
MMC_SEND_OP_COND
0x1
MMC_ALL_SEND_CID
0x2
MMC_SET_RELATIVE_ADDR
0x3
MMC_SET_DSR
0x4
MMC_RESERVED_5
0x5
MMC_SWITCH
0x6
MMC_SELECT_DESELECT_CARD
0x7
MMC_SEND_EXT_CSD
0x8
MMC_SEND_CSD
0x9
MMC_SEND_CID
0xa
MMC_READ_DAT_UNTIL_STOP
0xb
MMC_STOP_TRANSMISSION
0xc
MMC_SEND_STATUS
0xd
MMC_BUSTEST_R
0xe
MMC_GO_INACTIVE_STATE
0xf
MMC_SET_BLOCKLEN
0x10
MMC_READ_SINGLE_BLOCK
0x11
MMC_READ_MULTIPLE_BLOCK
0x12
MMC_BUSTEST_W
0x13
MMC_WRITE_DAT_UNTIL_STOP
0x14
MMC_SET_BLOCK_COUNT
0x17
MMC_WRITE_BLOCK
0x18
MMC_WRITE_MULTIPLE_BLOCK
0x19
MMC_PROGRAM_CID
0x1a
MMC_PROGRAM_CSD
0x1b
MMC_SET_WRITE_PROT
0x1c
MMC_CLR_WRITE_PROT
0x1d
MMC_SEND_WRITE_PROT
0x1e
MMC_ERASE_GROUP_START
0x23
MMC_ERASE_GROUP_END
0x24
MMC_ERASE
0x26
MMC_FAST_IO
0x27
MMC_GO_IRQ_STATE
0x28
MMC_LOCK_UNLOCK
0x2a
MMC_APP_CMD
0x37
MMC_GEN_CMD
0x38
SD_GO_IDLE_STATE
0x0
SD_ALL_SEND_CID
0x2
SD_SEND_RELATIVE_ADDR
0x3
SD_SET_DSR
0x4
SD_IO_SEND_OP_COND
0x5
SD_SELECT_DESELECT_CARD
0x7
SD_SEND_CSD
0x9
SD_SEND_CID
0xa
SD_STOP_TRANSMISSION
0xc
SD_SEND_STATUS
0xd
SD_GO_INACTIVE_STATE
0xf
SD_SET_BLOCKLEN
0x10
SD_READ_SINGLE_BLOCK
0x11
SD_READ_MULTIPLE_BLOCK
0x12
SD_WRITE_BLOCK
0x18
SD_WRITE_MULTIPLE_BLOCK
0x19
SD_PROGRAM_CSD
0x1b
SD_SET_WRITE_PROT
0x1c
SD_CLR_WRITE_PROT
0x1d
SD_SEND_WRITE_PROT
0x1e
SD_ERASE_WR_BLK_START
0x20
SD_ERASE_WR_BLK_END
0x21
SD_ERASE_GROUP_START
0x23
SD_ERASE_GROUP_END
0x24
SD_ERASE
0x26
SD_LOCK_UNLOCK
0x2a
SD_IO_RW_DIRECT
0x34
SD_IO_RW_EXTENDED
0x35
SD_APP_CMD
0x37
SD_GEN_CMD
0x38
set
4
clr
8
tog
12
CMD1
CMD1
0x20
CMD_ARG
0
32
COMPREF
COMPREF
0x30
REFERENCE
0
32
COMPMASK
COMPMASK
0x40
MASK
0
32
TIMING
TIMING
0x50
TIMEOUT
16
16
CLOCK_DIVIDE
8
8
CLOCK_RATE
0
8
CTRL1
CTRL1
0x60
SDIO_IRQ
31
SDIO_IRQ_EN
30
RESP_ERR_IRQ
29
RESP_ERR_IRQ_EN
28
RESP_TIMEOUT_IRQ
27
RESP_TIMEOUT_IRQ_EN
26
DATA_TIMEOUT_IRQ
25
DATA_TIMEOUT_IRQ_EN
24
DATA_CRC_IRQ
23
DATA_CRC_IRQ_EN
22
FIFO_UNDERRUN_IRQ
21
FIFO_UNDERRUN_EN
20
CEATA_CCS_ERR_IRQ
19
CEATA_CCS_ERR_IRQ_EN
18
RECV_TIMEOUT_IRQ
17
RECV_TIMEOUT_IRQ_EN
16
FIFO_OVERRUN_IRQ
15
FIFO_OVERRUN_IRQ_EN
14
DMA_ENABLE
13
CEATA_CCS_ERR_EN
12
SLAVE_OUT_DISABLE
11
PHASE
10
POLARITY
9
SLAVE_MODE
8
WORD_LENGTH
4
4
RESERVED0
0x0
RESERVED1
0x1
RESERVED2
0x2
FOUR_BITS
0x3
EIGHT_BITS
0x7
SIXTEEN_BITS
0xf
SSP_MODE
0
4
SPI
0x0
SSI
0x1
SD_MMC
0x3
MS
0x4
CE_ATA
0x7
set
4
clr
8
tog
12
DATA
DATA
0x70
DATA
0
32
SDRESP0
SDRESP0
0x80
RESP0
0
32
SDRESP1
SDRESP1
0x90
RESP1
0
32
SDRESP2
SDRESP2
0xa0
RESP2
0
32
SDRESP3
SDRESP3
0xb0
RESP3
0
32
STATUS
STATUS
0xc0
PRESENT
31
MS_PRESENT
30
SD_PRESENT
29
CARD_DETECT
28
DMASENSE
21
DMATERM
20
DMAREQ
19
DMAEND
18
SDIO_IRQ
17
RESP_CRC_ERR
16
RESP_ERR
15
RESP_TIMEOUT
14
DATA_CRC_ERR
13
TIMEOUT
12
RECV_TIMEOUT_STAT
11
CEATA_CCS_ERR
10
FIFO_OVRFLW
9
FIFO_FULL
8
FIFO_EMPTY
5
FIFO_UNDRFLW
4
CMD_BUSY
3
DATA_BUSY
2
BUSY
0
DEBUG
DEBUG
0x100
DATACRC_ERR
28
4
DATA_STALL
27
DAT_SM
24
3
DSM_IDLE
0x0
DSM_WORD
0x2
DSM_CRC1
0x3
DSM_CRC2
0x4
DSM_END
0x5
MSTK_SM
20
4
MSTK_IDLE
0x0
MSTK_CKON
0x1
MSTK_BS1
0x2
MSTK_TPC
0x3
MSTK_BS2
0x4
MSTK_HDSHK
0x5
MSTK_BS3
0x6
MSTK_RW
0x7
MSTK_CRC1
0x8
MSTK_CRC2
0x9
MSTK_BS0
0xa
MSTK_END1
0xb
MSTK_END2W
0xc
MSTK_END2R
0xd
MSTK_DONE
0xe
CMD_OE
19
DMA_SM
16
3
DMA_IDLE
0x0
DMA_DMAREQ
0x1
DMA_DMAACK
0x2
DMA_STALL
0x3
DMA_BUSY
0x4
DMA_DONE
0x5
DMA_COUNT
0x6
MMC_SM
12
4
MMC_IDLE
0x0
MMC_CMD
0x1
MMC_TRC
0x2
MMC_RESP
0x3
MMC_RPRX
0x4
MMC_TX
0x5
MMC_CTOK
0x6
MMC_RX
0x7
MMC_CCS
0x8
MMC_PUP
0x9
MMC_WAIT
0xa
CMD_SM
10
2
CSM_IDLE
0x0
CSM_INDEX
0x1
CSM_ARG
0x2
CSM_CRC
0x3
SSP_CMD
9
SSP_RESP
8
SSP_RXD
0
8
VERSION
VERSION
0x110
MAJOR
24
8
MINOR
16
8
STEP
0
16
TIMROT
Timers/Rotary Interface
Timers and Rotary Decoder
TIMROT
0x80068000
ROTCTRL
ROTCTRL
0x0
SFTRST
31
CLKGATE
30
ROTARY_PRESENT
29
TIM3_PRESENT
28
TIM2_PRESENT
27
TIM1_PRESENT
26
TIM0_PRESENT
25
STATE
22
3
DIVIDER
16
6
RELATIVE
12
OVERSAMPLE
10
2
8X
0x0
4X
0x1
2X
0x2
1X
0x3
POLARITY_B
9
POLARITY_A
8
SELECT_B
4
3
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
SELECT_A
0
3
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
set
4
clr
8
tog
12
ROTCOUNT
ROTCOUNT
0x10
UPDOWN
0
16
TIMCTRLn
TIMCTRLn
0
3
0x20
0x20
IRQ
15
IRQ_EN
14
POLARITY
8
UPDATE
7
RELOAD
6
PRESCALE
4
2
DIV_BY_1
0x0
DIV_BY_2
0x1
DIV_BY_4
0x2
DIV_BY_8
0x3
SELECT
0
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
set
4
clr
8
tog
12
TIMCOUNTn
TIMCOUNTn
0
3
0x30
0x20
RUNNING_COUNT
16
16
FIXED_COUNT
0
16
TIMCTRL3
TIMCTRL3
0x80
TEST_SIGNAL
16
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
IRQ
15
IRQ_EN
14
DUTY_VALID
10
DUTY_CYCLE
9
POLARITY
8
UPDATE
7
RELOAD
6
PRESCALE
4
2
DIV_BY_1
0x0
DIV_BY_2
0x1
DIV_BY_4
0x2
DIV_BY_8
0x3
SELECT
0
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
set
4
clr
8
tog
12
TIMCOUNT3
TIMCOUNT3
0x90
LOW_RUNNING_COUNT
16
16
HIGH_FIXED_COUNT
0
16
VERSION
VERSION
0xa0
MAJOR
24
8
MINOR
16
8
STEP
0
16
UARTAPP
Application UART
Application UART
UARTAPP
1
0x8006c000
0x8006e000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RUN
29
RX_SOURCE
28
RXTO_ENABLE
27
RXTIMEOUT
16
11
XFER_COUNT
0
16
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
RUN
28
XFER_COUNT
0
16
set
4
clr
8
tog
12
CTRL2
CTRL2
0x20
INVERT_RTS
31
INVERT_CTS
30
INVERT_TX
29
INVERT_RX
28
RTS_SEMAPHORE
27
DMAONERR
26
TXDMAE
25
RXDMAE
24
RXIFLSEL
20
3
NOT_EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
TXIFLSEL
16
3
EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
CTSEN
15
RTSEN
14
OUT2
13
OUT1
12
RTS
11
DTR
10
RXE
9
TXE
8
LBE
7
USE_LCR2
6
SIRLP
2
SIREN
1
UARTEN
0
set
4
clr
8
tog
12
LINECTRL
LINECTRL
0x30
BAUD_DIVINT
16
16
BAUD_DIVFRAC
8
6
SPS
7
WLEN
5
2
FEN
4
STP2
3
EPS
2
PEN
1
BRK
0
set
4
clr
8
tog
12
LINECTRL2
LINECTRL2
0x40
BAUD_DIVINT
16
16
BAUD_DIVFRAC
8
6
SPS
7
WLEN
5
2
FEN
4
STP2
3
EPS
2
PEN
1
set
4
clr
8
tog
12
INTR
INTR
0x50
OEIEN
26
BEIEN
25
PEIEN
24
FEIEN
23
RTIEN
22
TXIEN
21
RXIEN
20
DSRMIEN
19
DCDMIEN
18
CTSMIEN
17
RIMIEN
16
OEIS
10
BEIS
9
PEIS
8
FEIS
7
RTIS
6
TXIS
5
RXIS
4
DSRMIS
3
DCDMIS
2
CTSMIS
1
RIMIS
0
set
4
clr
8
tog
12
DATA
DATA
0x60
DATA
0
32
STAT
STAT
0x70
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
HISPEED
30
UNAVAILABLE
0x0
AVAILABLE
0x1
BUSY
29
CTS
28
TXFE
27
RXFF
26
TXFF
25
RXFE
24
RXBYTE_INVALID
20
4
OERR
19
BERR
18
PERR
17
FERR
16
RXCOUNT
0
16
DEBUG
DEBUG
0x80
TXDMARUN
5
RXDMARUN
4
TXCMDEND
3
RXCMDEND
2
TXDMARQ
1
RXDMARQ
0
VERSION
VERSION
0x90
MAJOR
24
8
MINOR
16
8
STEP
0
16
UARTDBG
Debug UART
Debug UART
UARTDBG
0x80070000
DR
DR
0x0
UNAVAILABLE
16
16
RESERVED
12
4
OE
11
BE
10
PE
9
FE
8
DATA
0
8
RSR_ECR
RSR_ECR
0x4
UNAVAILABLE
8
24
EC
4
4
OE
3
BE
2
PE
1
FE
0
FR
FR
0x18
UNAVAILABLE
16
16
RESERVED
9
7
RI
8
TXFE
7
RXFF
6
TXFF
5
RXFE
4
BUSY
3
DCD
2
DSR
1
CTS
0
ILPR
ILPR
0x20
UNAVAILABLE
8
24
ILPDVSR
0
8
IBRD
IBRD
0x24
UNAVAILABLE
16
16
BAUD_DIVINT
0
16
FBRD
FBRD
0x28
UNAVAILABLE
8
24
RESERVED
6
2
BAUD_DIVFRAC
0
6
LCR_H
LCR_H
0x2c
UNAVAILABLE
16
16
RESERVED
8
8
SPS
7
WLEN
5
2
FEN
4
STP2
3
EPS
2
PEN
1
BRK
0
CR
CR
0x30
UNAVAILABLE
16
16
CTSEN
15
RTSEN
14
OUT2
13
OUT1
12
RTS
11
DTR
10
RXE
9
TXE
8
LBE
7
RESERVED
3
4
SIRLP
2
SIREN
1
UARTEN
0
IFLS
IFLS
0x34
UNAVAILABLE
16
16
RESERVED
6
10
RXIFLSEL
3
3
NOT_EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
TXIFLSEL
0
3
EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
IMSC
IMSC
0x38
UNAVAILABLE
16
16
RESERVED
11
5
OEIM
10
BEIM
9
PEIM
8
FEIM
7
RTIM
6
TXIM
5
RXIM
4
DSRMIM
3
DCDMIM
2
CTSMIM
1
RIMIM
0
RIS
RIS
0x3c
UNAVAILABLE
16
16
RESERVED
11
5
OERIS
10
BERIS
9
PERIS
8
FERIS
7
RTRIS
6
TXRIS
5
RXRIS
4
DSRRMIS
3
DCDRMIS
2
CTSRMIS
1
RIRMIS
0
MIS
MIS
0x40
UNAVAILABLE
16
16
RESERVED
11
5
OEMIS
10
BEMIS
9
PEMIS
8
FEMIS
7
RTMIS
6
TXMIS
5
RXMIS
4
DSRMMIS
3
DCDMMIS
2
CTSMMIS
1
RIMMIS
0
ICR
ICR
0x44
UNAVAILABLE
16
16
RESERVED
11
5
OEIC
10
BEIC
9
PEIC
8
FEIC
7
RTIC
6
TXIC
5
RXIC
4
DSRMIC
3
DCDMIC
2
CTSMIC
1
RIMIC
0
DMACR
DMACR
0x48
UNAVAILABLE
16
16
RESERVED
3
13
DMAONERR
2
TXDMAE
1
RXDMAE
0
USBCTRL
USB Controller
USB High-Speed Host/Device Controller
USBCTRL
0x80080000
ID
ID
0x0
REV
16
8
ID_N
8
8
ID
0
8
GENERAL
GENERAL
0x4
SM
9
PHYM
6
3
PHYW
4
2
BWT
3
CLKC
1
2
RT
0
HOST
HOST
0x8
TTPER
24
8
TTASY
16
8
NPORT
1
3
HC
0
DEVICE
DEVICE
0xc
DEVEP
1
5
DC
0
TXBUF
TXBUF
0x10
TXLCR
31
TXCHANADD
16
8
TXADD
8
8
TXBURST
0
8
RXBUF
RXBUF
0x14
RXADD
8
8
RXBURST
0
8
TTTXBUF
TTTXBUF
0x18
TTTXBUF
0
32
TTRXBUF
TTRXBUF
0x1c
TTRXBUF
0
32
CAPLENGTH
CAPLENGTH
0x100
HCIVER
16
16
LENGTH
0
8
HCSPARAMS
HCSPARAMS
0x104
NPORTS
0
4
PPC
4
NPCC
8
4
NCC
12
4
PI
16
NPTT
20
4
NTT
24
4
HCCPARAMS
HCCPARAMS
0x108
ADDR64BITCAP
0
PGM_FRM_LIST_FLAG
1
ASYNC_PARK_CAP
2
ISO_SCH_THRESHOLD
8
8
DCIVERSION
DCIVERSION
0x120
DCIVER
0
16
DCCPARAMS
DCCPARAMS
0x124
HC
8
DC
7
DEN
0
5
USBCMD
USBCMD
0x140
RS
0
RST
1
FS0
2
FS1
3
PSE
4
ASE
5
IAA
6
LR
7
ASP0
8
ASP1
9
ASPE
11
FS2
15
ITC
16
8
USBSTS
USBSTS
0x144
UI
0
UEI
1
PCI
2
FRI
3
SEI
4
AAI
5
URI
6
SRI
7
SLI
8
ULPII
10
HCH
12
RCL
13
PS
14
AS
15
NAKI
16
USBINTR
USBINTR
0x148
UE
0
UEE
1
PCE
2
FRE
3
SEE
4
AAE
5
URE
6
SRE
7
SLE
8
ULPIE
10
NAKE
16
FRINDEX
FRINDEX
0x14c
LISTINDEX
3
11
UINDEX
0
3
CTRLDSSEGMENT
CTRLDSSEGMENT
0x150
EMPTY
0
32
PERIODICLISTBASE
PERIODICLISTBASE
0x154
BASEADDR
12
20
ASYNCLISTADDR
ASYNCLISTADDR
0x158
ASYBASE
5
27
TTCTRL
TTCTRL
0x15c
TTHA
24
7
BURSTSIZE
BURSTSIZE
0x160
TX
8
8
RX
0
8
TXFILLTUNING
TXFILLTUNING
0x164
TXFIFOTHRES
16
6
TXSCHEALTH
8
5
TXSCHOH
0
8
TXTTFILLTUNING
TXTTFILLTUNING
0x168
EMPTY
0
32
ULPI
ULPI
0x170
WAKEUP
31
RUN
30
RDWR
29
ERROR
28
SYNC
27
PORT
24
3
ADDR
16
8
DATARD
8
8
DATAWR
0
8
VFRAME
VFRAME
0x174
EMPTY
0
32
EPNAK
EPNAK
0x178
EPTN
16
16
EPRN
0
16
EPNAKEN
EPNAKEN
0x17c
EPTNE
16
16
EPRNE
0
16
CONFIGFLAG
CONFIGFLAG
0x180
FLAG
0
PORTSC1
PORTSC1
0x184
PTS
30
2
UTMI
0x0
PHIL
0x1
ULPI
0x2
SERIAL
0x3
STS
29
PTW
28
PSPD
26
2
FULL
0x0
LO
0x1
HI
0x2
PFSC
24
PHCD
23
WKOC
22
WKDS
21
WKCN
20
PTC
16
4
DISABLE
0x0
J
0x1
K
0x2
SE0orNAK
0x3
Packet
0x4
ForceEnableHS
0x5
ForceEnableFS
0x6
ForceEnableLS
0x7
PIC
14
2
OFF
0x0
AMBER
0x1
GREEN
0x2
UNDEF
0x3
PO
13
PP
12
LS
10
2
SE0
0x0
K
0x1
J
0x2
HSP
9
PR
8
SUSP
7
FPR
6
OCC
5
OCA
4
PEC
3
PE
2
CSC
1
CCS
0
OTGSC
OTGSC
0x1a4
DPIE
30
ONEMSE
29
BSEIE
28
BSVIE
27
ASVIE
26
AVVIE
25
IDIE
24
DPIS
22
ONEMSS
21
BSEIS
20
BSVIS
19
ASVIS
18
AVVIS
17
IDIS
16
DPS
14
ONEMST
13
BSE
12
BSV
11
ASV
10
AVV
9
ID
8
HABA
7
HADP
6
IDPU
5
DP
4
OT
3
HAAR
2
VC
1
VD
0
USBMODE
USBMODE
0x1a8
SDIS
4
SLOM
3
ES
2
CM
0
2
IDLE
0x0
DEVICE
0x2
HOST
0x3
ENDPTSETUPSTAT
ENDPTSETUPSTAT
0x1ac
STS
0
16
ENDPTPRIME
ENDPTPRIME
0x1b0
PETB
16
16
PERB
0
16
ENDPTFLUSH
ENDPTFLUSH
0x1b4
FETB
16
16
FERB
0
16
ENDPTSTATUS
ENDPTSTATUS
0x1b8
ETBR
16
16
ERBR
0
16
ENDPTCOMPLETE
ENDPTCOMPLETE
0x1bc
ETCE
16
16
ERCE
0
16
ENDPTCTRLn
ENDPTCTRLn
0
5
0x1c0
0x4
TXE
23
TXR
22
TXI
21
TXT
18
2
ISOCHRONOUS
0x1
BULK
0x2
INT
0x3
TXS
16
RXE
7
RXR
6
RXI
5
RXT
2
2
RXS
0
USBPHY
USB Physical Interface
Integrated USB 2.0 PHY
USBPHY
0x8007c000
PWD
PWD
0x0
RXPWDRX
20
RXPWDDIFF
19
RXPWD1PT1
18
RXPWDENV
17
TXPWDCOMP
14
TXPWDVBG
13
TXPWDV2I
12
TXPWDIBIAS
11
TXPWDFS
10
set
4
clr
8
tog
12
TX
TX
0x10
USBPHY_TX_EDGECTRL
26
3
USBPHY_TX_SYNC_INVERT
25
USBPHY_TX_SYNC_MUX
24
TXCMPOUT_STATUS
23
TXENCAL45DP
21
TXCAL45DP
16
4
TXENCAL45DN
13
TXCAL45DN
8
4
TXCALIBRATE
7
D_CAL
0
4
set
4
clr
8
tog
12
RX
RX
0x20
RXDBYPASS
22
DISCONADJ
4
2
ENVADJ
0
2
set
4
clr
8
tog
12
CTRL
CTRL
0x30
SFTRST
31
CLKGATE
30
UTMI_SUSPENDM
29
HOST_FORCE_LS_SE0
28
DATA_ON_LRADC
13
DEVPLUGIN_IRQ
12
ENIRQDEVPLUGIN
11
RESUME_IRQ
10
ENIRQRESUMEDETECT
9
ENOTGIDDETECT
7
DEVPLUGIN_POLARITY
5
ENDEVPLUGINDETECT
4
HOSTDISCONDETECT_IRQ
3
ENIRQHOSTDISCON
2
ENHOSTDISCONDETECT
1
ENHSPRECHARGEXMIT
0
set
4
clr
8
tog
12
STATUS
STATUS
0x40
RESUME_STATUS
10
OTGID_STATUS
8
DEVPLUGIN_STATUS
6
HOSTDISCONDETECT_STATUS
3
DEBUG
DEBUG
0x50
CLKGATE
30
HOST_RESUME_DEBUG
29
SQUELCHRESETLENGTH
25
4
ENSQUELCHRESET
24
SQUELCHRESETCOUNT
16
5
ENTX2RXCOUNT
12
TX2RXCOUNT
8
4
ENHSTPULLDOWN
4
2
HSTPULLDOWN
2
2
DEBUG_INTERFACE_HOLD
1
OTGIDPIOLOCK
0
set
4
clr
8
tog
12
DEBUG0_STATUS
DEBUG0_STATUS
0x60
SQUELCH_COUNT
26
6
UTMI_RXERROR_FAIL_COUNT
16
10
LOOP_BACK_FAIL_COUNT
0
16
DEBUG1
DEBUG1
0x70
ENTAILADJVD
13
2
ENTX2TX
12
PLL_IS_240
8
DBG_ADDRESS
0
4
set
4
clr
8
tog
12
VERSION
VERSION
0x80
MAJOR
24
8
MINOR
16
8
STEP
0
16