1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
|
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (c) 2008 by Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef _MC13783_H_
#define _MC13783_H_
enum mc13783_regs_enum
{
MC13783_INTERRUPT_STATUS0 = 0x00,
MC13783_INTERRUPT_MASK0,
MC13783_INTERRUPT_SENSE0,
MC13783_INTERRUPT_STATUS1,
MC13783_INTERRUPT_MASK1,
MC13783_INTERRUPT_SENSE1,
MC13783_POWER_UP_MODE_SENSE,
MC13783_IDENTIFICATION,
MC13783_SEMAPHORE,
MC13783_ARBITRATION_PERIPHERAL_AUDIO,
MC13783_ARBITRATION_SWITCHERS,
MC13783_ARBITRATION_REGULATORS0,
MC13783_ARBITRATION_REGULATORS1,
MC13783_POWER_CONTROL0,
MC13783_POWER_CONTROL1,
MC13783_POWER_CONTROL2,
MC13783_REGEN_ASSIGNMENT,
MC13783_CONTROL_SPARE,
MC13783_MEMORYA,
MC13783_MEMORYB,
MC13783_RTC_TIME,
MC13783_RTC_ALARM,
MC13783_RTC_DAY,
MC13783_RTC_DAY_ALARM,
MC13783_SWITCHERS0,
MC13783_SWITCHERS1,
MC13783_SWITCHERS2,
MC13783_SWITCHERS3,
MC13783_SWITCHERS4,
MC13783_SWITCHERS5,
MC13783_REGULATOR_SETTING0,
MC13783_REGULATOR_SETTING1,
MC13783_REGULATOR_MODE0,
MC13783_REGULATOR_MODE1,
MC13783_POWER_MISCELLANEOUS,
MC13783_POWER_SPARE,
MC13783_AUDIO_RX0,
MC13783_AUDIO_RX1,
MC13783_AUDIO_TX,
MC13783_SSI_NETWORK,
MC13783_AUDIO_CODEC,
MC13783_AUDIO_STEREO_CODEC,
MC13783_AUDIO_SPARE,
MC13783_ADC0,
MC13783_ADC1,
MC13783_ADC2,
MC13783_ADC3,
MC13783_ADC4,
MC13783_CHARGER,
MC13783_USB0,
MC13783_CHARGER_USB1,
MC13783_LED_CONTROL0,
MC13783_LED_CONTROL1,
MC13783_LED_CONTROL2,
MC13783_LED_CONTROL3,
MC13783_LED_CONTROL4,
MC13783_LED_CONTROL5,
MC13783_SPARE,
MC13783_TRIM0,
MC13783_TRIM1,
MC13783_TEST0,
MC13783_TEST1,
MC13783_TEST2,
MC13783_TEST3,
MC13783_NUM_REGS,
};
/* INTERRUPT_STATUS0, INTERRUPT_MASK0, INTERRUPT_SENSE0 */
#define MC13783_ADCDONE (1 << 0) /* x */
#define MC13783_ADCBISDONE (1 << 1) /* x */
#define MC13783_TS (1 << 2) /* x */
#define MC13783_WHIGH (1 << 3) /* x */
#define MC13783_WLOW (1 << 4) /* x */
#define MC13783_CHGDET (1 << 6)
#define MC13783_CHGOV (1 << 7)
#define MC13783_CHGREV (1 << 8)
#define MC13783_CHGSHORT (1 << 9)
#define MC13783_CCCV (1 << 10)
#define MC13783_CHGCURR (1 << 11)
#define MC13783_BPONI (1 << 12)
#define MC13783_LOBATL (1 << 13)
#define MC13783_LOBATH (1 << 14)
#define MC13783_UDP (1 << 15)
#define MC13783_USB4V4 (1 << 16)
#define MC13783_USB2V0 (1 << 17)
#define MC13783_USB0V8 (1 << 18)
#define MC13783_IDFLOAT (1 << 19)
#define MC13783_SE1 (1 << 21)
#define MC13783_CKDET (1 << 22)
#define MC13783_UDM (1 << 23)
/* x = no sense bit */
/* INTERRUPT_STATUS1, INTERRUPT_MASK1, INTERRUPT_SENSE1 */
#define MC13783_1HZ (1 << 0) /* x */
#define MC13783_TODA (1 << 1) /* x */
#define MC13783_ONOFD1 (1 << 3) /* ON1B */
#define MC13783_ONOFD2 (1 << 4) /* ON2B */
#define MC13783_ONOFD3 (1 << 5) /* ON3B */
#define MC13783_SYSRST (1 << 6) /* x */
#define MC13783_RTCRST (1 << 7) /* x */
#define MC13783_PCI (1 << 8) /* x */
#define MC13783_WARM (1 << 9) /* x */
#define MC13783_MEMHLD (1 << 10) /* x */
#define MC13783_PWRRDY (1 << 11)
#define MC13783_THWARNL (1 << 12)
#define MC13783_THWARNH (1 << 13)
#define MC13783_CLK (1 << 14)
#define MC13783_SEMAF (1 << 15) /* x */
#define MC13783_MC2B (1 << 17)
#define MC13783_HSDET (1 << 18)
#define MC13783_HSL (1 << 19)
#define MC13783_ALSPTH (1 << 20)
#define MC13783_AHSSHORT (1 << 21)
/* x = no sense bit */
/* POWER_UP_MODE_SENSE */
#define MC13783_ICTESTS (1 << 0)
#define MC13783_CLKSELS (1 << 1)
#define MC13783_PUMS1Sr(r) (((r) >> 2) & 0x3)
#define MC13783_PUMS2S (((r) >> 4) & 0x3)
#define MC13783_PUMS3S (((r) >> 6) & 0x3)
#define PUMS_LOW 0x0
#define PUMS_OPEN 0x1
#define PUMS_HIGH 0x2
#define MC13783_CHRGMOD0Sr(r) (((r) >> 8) & 0x3)
#define MC13783_CHRGMOD1Sr(r) (((r) >> 10) & 0x3)
#define CHRGMOD_LOW 0x0
#define CHRGMOD_OPEN 0x1
#define CHRGMOD_HIGH 0x3
#define MC13783_UMODSr(r) (((r) >> 12) & 0x3)
#define UMODS0_LOW_UMODS1_LOW 0x0
#define UMODS0_OPEN_UMODS1_LOW 0x1
#define UMODS0_DONTCARE_UMODS1_HIGH 0x2
#define UMODS0_HIGH_UMODS1_LOW 0x3
#define MC13783_USBEN (1 << 14)
#define MC13783_SW1ABS (1 << 15)
#define MC13783_SW2ABS (1 << 16)
/* IDENTIFICATION */
/* SEMAPHORE */
/* ARBITRATION_PERIPHERAL_AUDIO */
/* ARBITRATION_SWITCHERS */
/* ARBITRATION_REGULATORS0 */
/* ARBITRATION_REGULATORS1 */
/* POWER_CONTROL0 */
#define MC13783_USEROFFSPI (1 << 3)
/* POWER_CONTROL1 */
/* POWER_CONTROL2 */
/* REGEN_ASSIGNMENT */
/* MEMORYA */
/* MEMORYB */
/* RTC_TIME */
/* RTC_ALARM */
/* RTC_DAY */
/* RTC_DAY_ALARM */
/* SWITCHERS0 */
/* SWITCHERS1 */
/* SWITCHERS2 */
/* SWITCHERS3 */
/* SWITCHERS4 */
/* SWITCHERS5 */
/* REGULATOR_SETTING0 */
/* REGULATOR_SETTING1 */
/* REGULATOR_MODE0 */
/* REGULATOR_MODE1 */
/* POWER_MISCELLANEOUS */
/* AUDIO_RX0 */
/* AUDIO_RX1 */
/* AUDIO_TX */
/* SSI_NETWORK */
/* AUDIO_CODEC */
/* AUDIO_STEREO_CODEC */
/* ADC0 */
#define MC13783_LICELLCON (1 << 0)
#define MC13783_CHRGICON (1 << 1)
#define MC13783_BATICON (1 << 2)
#define MC13783_RTHEN (1 << 3)
#define MC13783_DTHEN (1 << 4)
#define MC13783_UIDEN (1 << 5)
#define MC13783_ADOUTEN (1 << 6)
#define MC13783_ADOUTPER (1 << 7)
#define MC13783_ADREFEN (1 << 10)
#define MC13783_ADREFMODE (1 << 11)
#define MC13783_TSMODw(w) ((w) << 12)
#define MC13783_TSMODr(r) (((r) >> 12) & 0x3)
#define MC13783_CHRGRAWDIV (1 << 15)
#define MC13783_ADINC1 (1 << 16)
#define MC13783_ADINC2 (1 << 17)
#define MC13783_WCOMP (1 << 18)
#define MC13783_ADCBIS0 (1 << 23)
/* ADC1 */
#define MC13783_ADEN (1 << 0)
#define MC13783_RAND (1 << 1)
#define MC13783_ADSEL (1 << 3)
#define MC13783_TRIGMASK (1 << 4)
#define MC13783_ADA1w(w) ((w) << 5)
#define MC13783_ADA1r(r) (((r) >> 5) & 0x3)
#define MC13783_ADA2w(w) ((w) << 8)
#define MC13783_ADA2r(r) (((r) >> 8) & 0x3)
#define MC13783_ATOw(w) ((w) << 11)
#define MC13783_ATOr(r) (((r) >> 11) & 0xff)
#define MC13783_ATOX (1 << 19)
#define MC13783_ASC (1 << 20)
#define MC13783_ADTRIGIGN (1 << 21)
#define MC13783_ADONESHOT (1 << 22)
#define MC13783_ADCBIS1 (1 << 23)
/* ADC2 */
#define MC13783_ADD1r(r) (((r) >> 2) & 0x3ff)
#define MC13783_ADD2r(r) (((r) >> 14) & 0x3ff)
/* ADC3 */
#define MC13783_WHIGHw(w) ((w) << 0)
#define MC13783_WHIGHr(r) ((r) & 0x3f)
#define MC13783_ICIDr(r) (((r) >> 6) & 0x3)
#define MC13783_WLOWw(w) ((w) << 9)
#define MC13783_WLOWr(r) (((r) >> 9) & 0x3f)
#define MC13783_ADCBIS2 (1 << 23)
/* ADC4 */
#define MC13783_ADCBIS1r(r) (((r) >> 2) & 0x3ff)
#define MC13783_ADCBIS2r(r) (((r) >> 14) & 0x3ff)
/* CHARGER */
/* USB0 */
/* CHARGER_USB1 */
/* LED_CONTROL0 */
#define MC13783_LEDEN (1 << 0)
/* LED_CONTROL1 */
/* LED_CONTROL2 */
/* LED_CONTROL3 */
/* LED_CONTROL4 */
/* LED_CONTROL5 */
/* TRIM0 */
/* TRIM1 */
/* TEST0 */
/* TEST1 */
/* TEST2 */
/* TEST3 */
void mc13783_init(void);
uint32_t mc13783_set(unsigned address, uint32_t bits);
uint32_t mc13783_clear(unsigned address, uint32_t bits);
int mc13783_write(unsigned address, uint32_t data);
int mc13783_write_multiple(unsigned start, const uint32_t *buffer, int count);
int mc13783_write_regset(const unsigned char *regs, const uint32_t *data, int count);
uint32_t mc13783_read(unsigned address);
int mc13783_read_multiple(unsigned start, uint32_t *buffer, int count);
int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer, int count);
void mc13783_alarm_start(void);
#endif /* _MC13783_H_ */
|
