summaryrefslogtreecommitdiffstats
path: root/firmware/export/rk27xx_codec.h
blob: 28ab4730d8b307ce261d6f6e2f280163957b3444 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * $Id$
 *
 * Driver for internal Rockchip rk27xx audio codec
 * (shCODlp-100.01-HD IP core from Dolphin)
 *
 * Copyright (c) 2011 Marcin Bukat
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef _RK27XX_CODEC_H_
#define _RK27XX_CODEC_H_

#define AUDIOHW_CAPS    (BASS_CAP | TREBLE_CAP | LIN_GAIN_CAP | MIC_GAIN_CAP)

AUDIOHW_SETTING(VOLUME,     "dB", 0,  1,   -34,    4, -25)
#ifdef HAVE_RECORDING /* disabled for now */
AUDIOHW_SETTING(LEFT_GAIN,  "dB", 2, 75, -1725, 3000,   0)
AUDIOHW_SETTING(RIGHT_GAIN, "dB", 2, 75, -1725, 3000,   0)
AUDIOHW_SETTING(MIC_GAIN,   "dB", 0,  1,     0,   20,  20)
#endif /* HAVE_RECORDING */

#define CODEC_I2C_ADDR 0x4e

/* registers */
#define AICR  0x00     /* Audio Interface Control    */
#define DAC_SERIAL     (1<<3)
#define ADC_SERIAL     (1<<2)
#define DAC_I2S        (1<<1)
#define ADC_I2S        (1<<0)

#define CR1   0x02     /* Control Register 1         */
#define SB_MICBIAS     (1<<7)
#define CR1_MONO       (1<<6)
#define DAC_MUTE       (1<<5)
#define HP_DIS         (1<<4)
#define DACSEL         (1<<3)
#define BYPASS1        (1<<2)
#define BYPASS2        (1<<1)
#define SIDETONE       (1<<0)

#define CR2   0x04     /* Control Register 2         */
#define DAC_DEEMP      (1<<7)
#define ADC_HPF        (1<<2)
#define INSEL_MIX      (3<<0)
#define INSEL_MIC      (2<<0)
#define INSEL_LINE2    (1<<0)
#define INSEL_LINE1    (0<<0)

#define CCR1  0x06     /* Control Clock Register 1   */
#define CRYSTAL_16M    (1<<0)
#define CRYSTAL_12M    (0<<0)

#define CCR2  0x08     /* Control Clock Register 2   */
#define FREQ8000       0x0a
#define FREQ9600       0x09
#define FREQ11025      0x08
#define FREQ12000      0x07
#define FREQ16000      0x06
#define FREQ22050      0x05
#define FREQ24000      0x04
#define FREQ32000      0x03
#define FREQ44100      0x02
#define FREQ48000      0x01
#define FREQ96000      0x00

#define PMR1  0x0a     /* Power Mode Register 1      */
#define SB_DAC         (1<<7)
#define SB_OUT         (1<<6)
#define SB_MIX         (1<<5)
#define SB_ADC         (1<<4)
#define SB_IN1         (1<<3)
#define SB_IN2         (1<<2)
#define SB_MIC         (1<<1)
#define SB_IND         (1<<0)

#define PMR2  0x0c     /* Power Mode Register 1      */
#define LRGI           (1<<7)
#define RLGI           (1<<6)
#define LRGOD          (1<<5)
#define RLGOD          (1<<4)
#define GIM            (1<<3)
#define SB_MC          (1<<2)
#define SB             (1<<1)
#define SB_SLEEP       (1<<0)

#define CRR   0x0e     /* Control Ramp Register      */
#define RATIO_8        (3<<5)
#define RATIO_4        (2<<5)
#define RATIO_2        (1<<5)
#define RATIO_1        (0<<5)
#define KFAST_32       (5<<2)
#define KFAST_16       (4<<2)
#define KFAST_8        (3<<2)
#define KFAST_4        (2<<2)
#define KFAST_2        (1<<2)
#define KFAST_1        (0<<2)
#define THRESHOLD_128  (3<<0)
#define THRESHOLD_64   (2<<0)
#define THRESHOLD_32   (1<<0)
#define THRESHOLD_0    (0<<0)

#define ICR   0x10     /* Interrupt Control Register */
#define IRQ_LOW_PULSE  (3<<6)
#define IRQ_HIGH_PULSE (2<<6)
#define IRQ_LOW        (1<<6)
#define IRQ_HIGH       (0<<6)
#define JACK_MASK      (1<<5)
#define CCMC_MASK      (1<<4)
#define RUD_MASK       (1<<3)
#define RDD_MASK       (1<<2)
#define GUD_MASK       (1<<1)
#define GDD_MASK       (1<<0)

#define IFR   0x12     /* Interrupt Flag Register    */
#define JACK           (1<<6)
#define JACK_EVENT     (1<<5)
#define CCMC           (1<<4)
#define RAMP_UP_DONE   (1<<3)
#define RAMP_DOWN_DONE (1<<2)
#define GAIN_UP_DONE   (1<<1)
#define GAIN_DOWN_DONE (1<<0)

#define CGR1  0x14     /* Control Gain Register 1 (DAC mixing)      */

#define CGR2  0x16     /* Control Gain Register 2 (LINE1 mixing)    */
#define LRGOB1         (1<<7)
#define RLGOB1         (1<<6)

#define CGR3  0x18     /* Control Gain Register 3 (LINE1 mixing)    */

#define CGR4  0x1a     /* Control Gain Register 4 (LINE2 mixing)    */
#define LRGOB2         (1<<7)
#define RLGOB2         (1<<6)

#define CGR5  0x1c     /* Control Gain Register 5 (LINE2 mixing)    */

#define CGR6  0x1e     /* Control Gain Register 6 (MIC mixing)      */
#define LRGOS          (1<<7)
#define RLGOS          (1<<6)

#define CGR7  0x20     /* Control Gain Register 7 (MIC mixing)      */

#define CGR8  0x22     /* Control Gain Register 8 (OUT STAGE gain)  */
#define LRGO           (1<<7)
#define RLGO           (1<<6)

#define CGR9  0x24     /* Control Gain Register 9 (OUT STAGE gain)  */

#define CGR10 0x26     /* Control Gain Register 10 (ADC input gain) */

#define TR1   0x28     /* undocumented */
#define NOSC           (1<<1)

#define TR2   0x2a     /* undocumented */

#endif /* _RK27XX_CODEC_H_ */