summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/imx233/regs/imx233/regs-dcp.h
blob: 9428f978987b104377b217bc731bc4c64702be8e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 2.1.7
 * XML versions: imx233:3.2.0
 *
 * Copyright (C) 2013 by Amaury Pouly
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN__IMX233__DCP__H__
#define __HEADERGEN__IMX233__DCP__H__

#define REGS_DCP_BASE (0x80028000)

#define REGS_DCP_VERSION "3.2.0"

/**
 * Register: HW_DCP_CTRL
 * Address: 0
 * SCT: yes
*/
#define HW_DCP_CTRL                                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0))
#define HW_DCP_CTRL_SET                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4))
#define HW_DCP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8))
#define HW_DCP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc))
#define BP_DCP_CTRL_SFTRST                          31
#define BM_DCP_CTRL_SFTRST                          0x80000000
#define BF_DCP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
#define BP_DCP_CTRL_CLKGATE                         30
#define BM_DCP_CTRL_CLKGATE                         0x40000000
#define BF_DCP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) << 29) & 0x20000000)
#define BF_DCP_CTRL_PRESENT_CRYPTO_V(v)             ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000)
#define BP_DCP_CTRL_PRESENT_CSC                     28
#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) << 28) & 0x10000000)
#define BF_DCP_CTRL_PRESENT_CSC_V(v)                ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000)
#define BP_DCP_CTRL_RSVD1                           24
#define BM_DCP_CTRL_RSVD1                           0xf000000
#define BF_DCP_CTRL_RSVD1(v)                        (((v) << 24) & 0xf000000)
#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) << 23) & 0x800000)
#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) << 22) & 0x400000)
#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) << 21) & 0x200000)
#define BP_DCP_CTRL_RSVD0                           9
#define BM_DCP_CTRL_RSVD0                           0x1ffe00
#define BF_DCP_CTRL_RSVD0(v)                        (((v) << 9) & 0x1ffe00)
#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) << 8) & 0x100)
#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) << 0) & 0xff)
#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)   ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff)

/**
 * Register: HW_DCP_STAT
 * Address: 0x10
 * SCT: yes
*/
#define HW_DCP_STAT                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0))
#define HW_DCP_STAT_SET                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4))
#define HW_DCP_STAT_CLR                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8))
#define HW_DCP_STAT_TOG                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc))
#define BP_DCP_STAT_RSVD2               29
#define BM_DCP_STAT_RSVD2               0xe0000000
#define BF_DCP_STAT_RSVD2(v)            (((v) << 29) & 0xe0000000)
#define BP_DCP_STAT_OTP_KEY_READY       28
#define BM_DCP_STAT_OTP_KEY_READY       0x10000000
#define BF_DCP_STAT_OTP_KEY_READY(v)    (((v) << 28) & 0x10000000)
#define BP_DCP_STAT_CUR_CHANNEL         24
#define BM_DCP_STAT_CUR_CHANNEL         0xf000000
#define BV_DCP_STAT_CUR_CHANNEL__None   0x0
#define BV_DCP_STAT_CUR_CHANNEL__CH0    0x1
#define BV_DCP_STAT_CUR_CHANNEL__CH1    0x2
#define BV_DCP_STAT_CUR_CHANNEL__CH2    0x3
#define BV_DCP_STAT_CUR_CHANNEL__CH3    0x4
#define BV_DCP_STAT_CUR_CHANNEL__CSC    0x8
#define BF_DCP_STAT_CUR_CHANNEL(v)      (((v) << 24) & 0xf000000)
#define BF_DCP_STAT_CUR_CHANNEL_V(v)    ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000)
#define BP_DCP_STAT_READY_CHANNELS      16
#define BM_DCP_STAT_READY_CHANNELS      0xff0000
#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1
#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2
#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4
#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8
#define BF_DCP_STAT_READY_CHANNELS(v)   (((v) << 16) & 0xff0000)
#define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000)
#define BP_DCP_STAT_RSVD1               9
#define BM_DCP_STAT_RSVD1               0xfe00
#define BF_DCP_STAT_RSVD1(v)            (((v) << 9) & 0xfe00)
#define BP_DCP_STAT_CSCIRQ              8
#define BM_DCP_STAT_CSCIRQ              0x100
#define BF_DCP_STAT_CSCIRQ(v)           (((v) << 8) & 0x100)
#define BP_DCP_STAT_RSVD0               4
#define BM_DCP_STAT_RSVD0               0xf0
#define BF_DCP_STAT_RSVD0(v)            (((v) << 4) & 0xf0)
#define BP_DCP_STAT_IRQ                 0
#define BM_DCP_STAT_IRQ                 0xf
#define BF_DCP_STAT_IRQ(v)              (((v) << 0) & 0xf)

/**
 * Register: HW_DCP_CHANNELCTRL
 * Address: 0x20
 * SCT: yes
*/
#define HW_DCP_CHANNELCTRL                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0))
#define HW_DCP_CHANNELCTRL_SET                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4))
#define HW_DCP_CHANNELCTRL_CLR                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8))
#define HW_DCP_CHANNELCTRL_TOG                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc))
#define BP_DCP_CHANNELCTRL_RSVD                         19
#define BM_DCP_CHANNELCTRL_RSVD                         0xfff80000
#define BF_DCP_CHANNELCTRL_RSVD(v)                      (((v) << 19) & 0xfff80000)
#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) << 17) & 0x60000)
#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)            ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000)
#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) << 16) & 0x10000)
#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) << 8) & 0xff00)
#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)   ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00)
#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) << 0) & 0xff)
#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)          ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff)

/**
 * Register: HW_DCP_CAPABILITY0
 * Address: 0x30
 * SCT: no
*/
#define HW_DCP_CAPABILITY0                      (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30))
#define BP_DCP_CAPABILITY0_DISABLE_DECRYPT      31
#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT      0x80000000
#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v)   (((v) << 31) & 0x80000000)
#define BP_DCP_CAPABILITY0_ENABLE_TZONE         30
#define BM_DCP_CAPABILITY0_ENABLE_TZONE         0x40000000
#define BF_DCP_CAPABILITY0_ENABLE_TZONE(v)      (((v) << 30) & 0x40000000)
#define BP_DCP_CAPABILITY0_RSVD                 12
#define BM_DCP_CAPABILITY0_RSVD                 0x3ffff000
#define BF_DCP_CAPABILITY0_RSVD(v)              (((v) << 12) & 0x3ffff000)
#define BP_DCP_CAPABILITY0_NUM_CHANNELS         8
#define BM_DCP_CAPABILITY0_NUM_CHANNELS         0xf00
#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)      (((v) << 8) & 0xf00)
#define BP_DCP_CAPABILITY0_NUM_KEYS             0
#define BM_DCP_CAPABILITY0_NUM_KEYS             0xff
#define BF_DCP_CAPABILITY0_NUM_KEYS(v)          (((v) << 0) & 0xff)

/**
 * Register: HW_DCP_CAPABILITY1
 * Address: 0x40
 * SCT: no
*/
#define HW_DCP_CAPABILITY1                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40))
#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) << 16) & 0xffff0000)
#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)         ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000)
#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) << 0) & 0xffff)
#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)       ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff)

/**
 * Register: HW_DCP_CONTEXT
 * Address: 0x50
 * SCT: no
*/
#define HW_DCP_CONTEXT          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50))
#define BP_DCP_CONTEXT_ADDR     0
#define BM_DCP_CONTEXT_ADDR     0xffffffff
#define BF_DCP_CONTEXT_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_KEY
 * Address: 0x60
 * SCT: no
*/
#define HW_DCP_KEY                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60))
#define BP_DCP_KEY_RSVD             8
#define BM_DCP_KEY_RSVD             0xffffff00
#define BF_DCP_KEY_RSVD(v)          (((v) << 8) & 0xffffff00)
#define BP_DCP_KEY_RSVD_INDEX       6
#define BM_DCP_KEY_RSVD_INDEX       0xc0
#define BF_DCP_KEY_RSVD_INDEX(v)    (((v) << 6) & 0xc0)
#define BP_DCP_KEY_INDEX            4
#define BM_DCP_KEY_INDEX            0x30
#define BF_DCP_KEY_INDEX(v)         (((v) << 4) & 0x30)
#define BP_DCP_KEY_RSVD_SUBWORD     2
#define BM_DCP_KEY_RSVD_SUBWORD     0xc
#define BF_DCP_KEY_RSVD_SUBWORD(v)  (((v) << 2) & 0xc)
#define BP_DCP_KEY_SUBWORD          0
#define BM_DCP_KEY_SUBWORD          0x3
#define BF_DCP_KEY_SUBWORD(v)       (((v) << 0) & 0x3)

/**
 * Register: HW_DCP_KEYDATA
 * Address: 0x70
 * SCT: no
*/
#define HW_DCP_KEYDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70))
#define BP_DCP_KEYDATA_DATA     0
#define BM_DCP_KEYDATA_DATA     0xffffffff
#define BF_DCP_KEYDATA_DATA(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PACKET0
 * Address: 0x80
 * SCT: no
*/
#define HW_DCP_PACKET0          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80))
#define BP_DCP_PACKET0_ADDR     0
#define BM_DCP_PACKET0_ADDR     0xffffffff
#define BF_DCP_PACKET0_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PACKET1
 * Address: 0x90
 * SCT: no
*/
#define HW_DCP_PACKET1                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90))
#define BP_DCP_PACKET1_TAG                      24
#define BM_DCP_PACKET1_TAG                      0xff000000
#define BF_DCP_PACKET1_TAG(v)                   (((v) << 24) & 0xff000000)
#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) << 23) & 0x800000)
#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) << 22) & 0x400000)
#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) << 21) & 0x200000)
#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) << 20) & 0x100000)
#define BP_DCP_PACKET1_KEY_WORDSWAP             19
#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) << 19) & 0x80000)
#define BP_DCP_PACKET1_KEY_BYTESWAP             18
#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) << 18) & 0x40000)
#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) << 17) & 0x20000)
#define BP_DCP_PACKET1_CONSTANT_FILL            16
#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) << 16) & 0x10000)
#define BP_DCP_PACKET1_HASH_OUTPUT              15
#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) << 15) & 0x8000)
#define BF_DCP_PACKET1_HASH_OUTPUT_V(v)         ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000)
#define BP_DCP_PACKET1_CHECK_HASH               14
#define BM_DCP_PACKET1_CHECK_HASH               0x4000
#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) << 14) & 0x4000)
#define BP_DCP_PACKET1_HASH_TERM                13
#define BM_DCP_PACKET1_HASH_TERM                0x2000
#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) << 13) & 0x2000)
#define BP_DCP_PACKET1_HASH_INIT                12
#define BM_DCP_PACKET1_HASH_INIT                0x1000
#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) << 12) & 0x1000)
#define BP_DCP_PACKET1_PAYLOAD_KEY              11
#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) << 11) & 0x800)
#define BP_DCP_PACKET1_OTP_KEY                  10
#define BM_DCP_PACKET1_OTP_KEY                  0x400
#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) << 10) & 0x400)
#define BP_DCP_PACKET1_CIPHER_INIT              9
#define BM_DCP_PACKET1_CIPHER_INIT              0x200
#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) << 9) & 0x200)
#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) << 8) & 0x100)
#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v)      ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100)
#define BP_DCP_PACKET1_ENABLE_BLIT              7
#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) << 7) & 0x80)
#define BP_DCP_PACKET1_ENABLE_HASH              6
#define BM_DCP_PACKET1_ENABLE_HASH              0x40
#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) << 6) & 0x40)
#define BP_DCP_PACKET1_ENABLE_CIPHER            5
#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) << 5) & 0x20)
#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) << 4) & 0x10)
#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) << 3) & 0x8)
#define BP_DCP_PACKET1_CHAIN                    2
#define BM_DCP_PACKET1_CHAIN                    0x4
#define BF_DCP_PACKET1_CHAIN(v)                 (((v) << 2) & 0x4)
#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) << 1) & 0x2)
#define BP_DCP_PACKET1_INTERRUPT                0
#define BM_DCP_PACKET1_INTERRUPT                0x1
#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) << 0) & 0x1)

/**
 * Register: HW_DCP_PACKET2
 * Address: 0xa0
 * SCT: no
*/
#define HW_DCP_PACKET2                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0))
#define BP_DCP_PACKET2_CIPHER_CFG               24
#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) << 24) & 0xff000000)
#define BP_DCP_PACKET2_RSVD                     20
#define BM_DCP_PACKET2_RSVD                     0xf00000
#define BF_DCP_PACKET2_RSVD(v)                  (((v) << 20) & 0xf00000)
#define BP_DCP_PACKET2_HASH_SELECT              16
#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) << 16) & 0xf0000)
#define BF_DCP_PACKET2_HASH_SELECT_V(v)         ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000)
#define BP_DCP_PACKET2_KEY_SELECT               8
#define BM_DCP_PACKET2_KEY_SELECT               0xff00
#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) << 8) & 0xff00)
#define BP_DCP_PACKET2_CIPHER_MODE              4
#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
#define BV_DCP_PACKET2_CIPHER_MODE__CBC         0x1
#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) << 4) & 0xf0)
#define BF_DCP_PACKET2_CIPHER_MODE_V(v)         ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0)
#define BP_DCP_PACKET2_CIPHER_SELECT            0
#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) << 0) & 0xf)
#define BF_DCP_PACKET2_CIPHER_SELECT_V(v)       ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf)

/**
 * Register: HW_DCP_PACKET3
 * Address: 0xb0
 * SCT: no
*/
#define HW_DCP_PACKET3          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0))
#define BP_DCP_PACKET3_ADDR     0
#define BM_DCP_PACKET3_ADDR     0xffffffff
#define BF_DCP_PACKET3_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PACKET4
 * Address: 0xc0
 * SCT: no
*/
#define HW_DCP_PACKET4          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0))
#define BP_DCP_PACKET4_ADDR     0
#define BM_DCP_PACKET4_ADDR     0xffffffff
#define BF_DCP_PACKET4_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PACKET5
 * Address: 0xd0
 * SCT: no
*/
#define HW_DCP_PACKET5          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0))
#define BP_DCP_PACKET5_COUNT    0
#define BM_DCP_PACKET5_COUNT    0xffffffff
#define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PACKET6
 * Address: 0xe0
 * SCT: no
*/
#define HW_DCP_PACKET6          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0))
#define BP_DCP_PACKET6_ADDR     0
#define BM_DCP_PACKET6_ADDR     0xffffffff
#define BF_DCP_PACKET6_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CHnCMDPTR
 * Address: 0x100+n*0x40
 * SCT: no
*/
#define HW_DCP_CHnCMDPTR(n)         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40))
#define BP_DCP_CHnCMDPTR_ADDR       0
#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CHnSEMA
 * Address: 0x110+n*0x40
 * SCT: no
*/
#define HW_DCP_CHnSEMA(n)           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40))
#define BP_DCP_CHnSEMA_RSVD2        24
#define BM_DCP_CHnSEMA_RSVD2        0xff000000
#define BF_DCP_CHnSEMA_RSVD2(v)     (((v) << 24) & 0xff000000)
#define BP_DCP_CHnSEMA_VALUE        16
#define BM_DCP_CHnSEMA_VALUE        0xff0000
#define BF_DCP_CHnSEMA_VALUE(v)     (((v) << 16) & 0xff0000)
#define BP_DCP_CHnSEMA_RSVD1        8
#define BM_DCP_CHnSEMA_RSVD1        0xff00
#define BF_DCP_CHnSEMA_RSVD1(v)     (((v) << 8) & 0xff00)
#define BP_DCP_CHnSEMA_INCREMENT    0
#define BM_DCP_CHnSEMA_INCREMENT    0xff
#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff)

/**
 * Register: HW_DCP_CHnSTAT
 * Address: 0x120+n*0x40
 * SCT: yes
*/
#define HW_DCP_CHnSTAT(n)                           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0))
#define HW_DCP_CHnSTAT_SET(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4))
#define HW_DCP_CHnSTAT_CLR(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8))
#define HW_DCP_CHnSTAT_TOG(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc))
#define BP_DCP_CHnSTAT_TAG                          24
#define BM_DCP_CHnSTAT_TAG                          0xff000000
#define BF_DCP_CHnSTAT_TAG(v)                       (((v) << 24) & 0xff000000)
#define BP_DCP_CHnSTAT_ERROR_CODE                   16
#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) << 16) & 0xff0000)
#define BF_DCP_CHnSTAT_ERROR_CODE_V(v)              ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000)
#define BP_DCP_CHnSTAT_RSVD0                        7
#define BM_DCP_CHnSTAT_RSVD0                        0xff80
#define BF_DCP_CHnSTAT_RSVD0(v)                     (((v) << 7) & 0xff80)
#define BP_DCP_CHnSTAT_ERROR_PAGEFAULT              6
#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT              0x40
#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v)           (((v) << 6) & 0x40)
#define BP_DCP_CHnSTAT_ERROR_DST                    5
#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) << 5) & 0x20)
#define BP_DCP_CHnSTAT_ERROR_SRC                    4
#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) << 4) & 0x10)
#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) << 3) & 0x8)
#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) << 2) & 0x4)
#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) << 1) & 0x2)
#define BP_DCP_CHnSTAT_RSVD_COMPLETE                0
#define BM_DCP_CHnSTAT_RSVD_COMPLETE                0x1
#define BF_DCP_CHnSTAT_RSVD_COMPLETE(v)             (((v) << 0) & 0x1)

/**
 * Register: HW_DCP_CHnOPTS
 * Address: 0x130+n*0x40
 * SCT: yes
*/
#define HW_DCP_CHnOPTS(n)                   (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0))
#define HW_DCP_CHnOPTS_SET(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4))
#define HW_DCP_CHnOPTS_CLR(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8))
#define HW_DCP_CHnOPTS_TOG(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc))
#define BP_DCP_CHnOPTS_RSVD                 16
#define BM_DCP_CHnOPTS_RSVD                 0xffff0000
#define BF_DCP_CHnOPTS_RSVD(v)              (((v) << 16) & 0xffff0000)
#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) << 0) & 0xffff)

/**
 * Register: HW_DCP_CSCCTRL0
 * Address: 0x300
 * SCT: yes
*/
#define HW_DCP_CSCCTRL0                         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0))
#define HW_DCP_CSCCTRL0_SET                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4))
#define HW_DCP_CSCCTRL0_CLR                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8))
#define HW_DCP_CSCCTRL0_TOG                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc))
#define BP_DCP_CSCCTRL0_RSVD1                   16
#define BM_DCP_CSCCTRL0_RSVD1                   0xffff0000
#define BF_DCP_CSCCTRL0_RSVD1(v)                (((v) << 16) & 0xffff0000)
#define BP_DCP_CSCCTRL0_CLIP                    15
#define BM_DCP_CSCCTRL0_CLIP                    0x8000
#define BF_DCP_CSCCTRL0_CLIP(v)                 (((v) << 15) & 0x8000)
#define BP_DCP_CSCCTRL0_UPSAMPLE                14
#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) << 14) & 0x4000)
#define BP_DCP_CSCCTRL0_SCALE                   13
#define BM_DCP_CSCCTRL0_SCALE                   0x2000
#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) << 13) & 0x2000)
#define BP_DCP_CSCCTRL0_ROTATE                  12
#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) << 12) & 0x1000)
#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) << 11) & 0x800)
#define BP_DCP_CSCCTRL0_DELTA                   10
#define BM_DCP_CSCCTRL0_DELTA                   0x400
#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) << 10) & 0x400)
#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI      0x1
#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) << 8) & 0x300)
#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300)
#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) << 4) & 0xf0)
#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0)
#define BP_DCP_CSCCTRL0_RSVD0                   1
#define BM_DCP_CSCCTRL0_RSVD0                   0xe
#define BF_DCP_CSCCTRL0_RSVD0(v)                (((v) << 1) & 0xe)
#define BP_DCP_CSCCTRL0_ENABLE                  0
#define BM_DCP_CSCCTRL0_ENABLE                  0x1
#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) << 0) & 0x1)

/**
 * Register: HW_DCP_CSCSTAT
 * Address: 0x310
 * SCT: yes
*/
#define HW_DCP_CSCSTAT                                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0))
#define HW_DCP_CSCSTAT_SET                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4))
#define HW_DCP_CSCSTAT_CLR                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8))
#define HW_DCP_CSCSTAT_TOG                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc))
#define BP_DCP_CSCSTAT_RSVD3                            24
#define BM_DCP_CSCSTAT_RSVD3                            0xff000000
#define BF_DCP_CSCSTAT_RSVD3(v)                         (((v) << 24) & 0xff000000)
#define BP_DCP_CSCSTAT_ERROR_CODE                       16
#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) << 16) & 0xff0000)
#define BF_DCP_CSCSTAT_ERROR_CODE_V(v)                  ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000)
#define BP_DCP_CSCSTAT_RSVD2                            7
#define BM_DCP_CSCSTAT_RSVD2                            0xff80
#define BF_DCP_CSCSTAT_RSVD2(v)                         (((v) << 7) & 0xff80)
#define BP_DCP_CSCSTAT_ERROR_PAGEFAULT                  6
#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT                  0x40
#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v)               (((v) << 6) & 0x40)
#define BP_DCP_CSCSTAT_ERROR_DST                        5
#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) << 5) & 0x20)
#define BP_DCP_CSCSTAT_ERROR_SRC                        4
#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) << 4) & 0x10)
#define BP_DCP_CSCSTAT_RSVD1                            3
#define BM_DCP_CSCSTAT_RSVD1                            0x8
#define BF_DCP_CSCSTAT_RSVD1(v)                         (((v) << 3) & 0x8)
#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) << 2) & 0x4)
#define BP_DCP_CSCSTAT_RSVD0                            1
#define BM_DCP_CSCSTAT_RSVD0                            0x2
#define BF_DCP_CSCSTAT_RSVD0(v)                         (((v) << 1) & 0x2)
#define BP_DCP_CSCSTAT_COMPLETE                         0
#define BM_DCP_CSCSTAT_COMPLETE                         0x1
#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) << 0) & 0x1)

/**
 * Register: HW_DCP_CSCOUTBUFPARAM
 * Address: 0x320
 * SCT: no
*/
#define HW_DCP_CSCOUTBUFPARAM               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320))
#define BP_DCP_CSCOUTBUFPARAM_RSVD1         24
#define BM_DCP_CSCOUTBUFPARAM_RSVD1         0xff000000
#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v)      (((v) << 24) & 0xff000000)
#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE    12
#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE    0xfff000
#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000)
#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE     0
#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE     0xfff
#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  (((v) << 0) & 0xfff)

/**
 * Register: HW_DCP_CSCINBUFPARAM
 * Address: 0x330
 * SCT: no
*/
#define HW_DCP_CSCINBUFPARAM                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330))
#define BP_DCP_CSCINBUFPARAM_RSVD1          12
#define BM_DCP_CSCINBUFPARAM_RSVD1          0xfffff000
#define BF_DCP_CSCINBUFPARAM_RSVD1(v)       (((v) << 12) & 0xfffff000)
#define BP_DCP_CSCINBUFPARAM_LINE_SIZE      0
#define BM_DCP_CSCINBUFPARAM_LINE_SIZE      0xfff
#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)   (((v) << 0) & 0xfff)

/**
 * Register: HW_DCP_CSCRGB
 * Address: 0x340
 * SCT: no
*/
#define HW_DCP_CSCRGB           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340))
#define BP_DCP_CSCRGB_ADDR      0
#define BM_DCP_CSCRGB_ADDR      0xffffffff
#define BF_DCP_CSCRGB_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CSCLUMA
 * Address: 0x350
 * SCT: no
*/
#define HW_DCP_CSCLUMA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350))
#define BP_DCP_CSCLUMA_ADDR     0
#define BM_DCP_CSCLUMA_ADDR     0xffffffff
#define BF_DCP_CSCLUMA_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CSCCHROMAU
 * Address: 0x360
 * SCT: no
*/
#define HW_DCP_CSCCHROMAU           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360))
#define BP_DCP_CSCCHROMAU_ADDR      0
#define BM_DCP_CSCCHROMAU_ADDR      0xffffffff
#define BF_DCP_CSCCHROMAU_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CSCCHROMAV
 * Address: 0x370
 * SCT: no
*/
#define HW_DCP_CSCCHROMAV           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370))
#define BP_DCP_CSCCHROMAV_ADDR      0
#define BM_DCP_CSCCHROMAV_ADDR      0xffffffff
#define BF_DCP_CSCCHROMAV_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_CSCCOEFF0
 * Address: 0x380
 * SCT: no
*/
#define HW_DCP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380))
#define BP_DCP_CSCCOEFF0_RSVD1          26
#define BM_DCP_CSCCOEFF0_RSVD1          0xfc000000
#define BF_DCP_CSCCOEFF0_RSVD1(v)       (((v) << 26) & 0xfc000000)
#define BP_DCP_CSCCOEFF0_C0             16
#define BM_DCP_CSCCOEFF0_C0             0x3ff0000
#define BF_DCP_CSCCOEFF0_C0(v)          (((v) << 16) & 0x3ff0000)
#define BP_DCP_CSCCOEFF0_UV_OFFSET      8
#define BM_DCP_CSCCOEFF0_UV_OFFSET      0xff00
#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 8) & 0xff00)
#define BP_DCP_CSCCOEFF0_Y_OFFSET       0
#define BM_DCP_CSCCOEFF0_Y_OFFSET       0xff
#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0xff)

/**
 * Register: HW_DCP_CSCCOEFF1
 * Address: 0x390
 * SCT: no
*/
#define HW_DCP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390))
#define BP_DCP_CSCCOEFF1_RSVD1      26
#define BM_DCP_CSCCOEFF1_RSVD1      0xfc000000
#define BF_DCP_CSCCOEFF1_RSVD1(v)   (((v) << 26) & 0xfc000000)
#define BP_DCP_CSCCOEFF1_C1         16
#define BM_DCP_CSCCOEFF1_C1         0x3ff0000
#define BF_DCP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x3ff0000)
#define BP_DCP_CSCCOEFF1_RSVD0      10
#define BM_DCP_CSCCOEFF1_RSVD0      0xfc00
#define BF_DCP_CSCCOEFF1_RSVD0(v)   (((v) << 10) & 0xfc00)
#define BP_DCP_CSCCOEFF1_C4         0
#define BM_DCP_CSCCOEFF1_C4         0x3ff
#define BF_DCP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x3ff)

/**
 * Register: HW_DCP_CSCCOEFF2
 * Address: 0x3a0
 * SCT: no
*/
#define HW_DCP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0))
#define BP_DCP_CSCCOEFF2_RSVD1      26
#define BM_DCP_CSCCOEFF2_RSVD1      0xfc000000
#define BF_DCP_CSCCOEFF2_RSVD1(v)   (((v) << 26) & 0xfc000000)
#define BP_DCP_CSCCOEFF2_C2         16
#define BM_DCP_CSCCOEFF2_C2         0x3ff0000
#define BF_DCP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x3ff0000)
#define BP_DCP_CSCCOEFF2_RSVD0      10
#define BM_DCP_CSCCOEFF2_RSVD0      0xfc00
#define BF_DCP_CSCCOEFF2_RSVD0(v)   (((v) << 10) & 0xfc00)
#define BP_DCP_CSCCOEFF2_C3         0
#define BM_DCP_CSCCOEFF2_C3         0x3ff
#define BF_DCP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x3ff)

/**
 * Register: HW_DCP_CSCCLIP
 * Address: 0x3d0
 * SCT: no
*/
#define HW_DCP_CSCCLIP              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3d0))
#define BP_DCP_CSCCLIP_RSVD1        24
#define BM_DCP_CSCCLIP_RSVD1        0xff000000
#define BF_DCP_CSCCLIP_RSVD1(v)     (((v) << 24) & 0xff000000)
#define BP_DCP_CSCCLIP_HEIGHT       12
#define BM_DCP_CSCCLIP_HEIGHT       0xfff000
#define BF_DCP_CSCCLIP_HEIGHT(v)    (((v) << 12) & 0xfff000)
#define BP_DCP_CSCCLIP_WIDTH        0
#define BM_DCP_CSCCLIP_WIDTH        0xfff
#define BF_DCP_CSCCLIP_WIDTH(v)     (((v) << 0) & 0xfff)

/**
 * Register: HW_DCP_CSCXSCALE
 * Address: 0x3e0
 * SCT: no
*/
#define HW_DCP_CSCXSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0))
#define BP_DCP_CSCXSCALE_RSVD1      26
#define BM_DCP_CSCXSCALE_RSVD1      0xfc000000
#define BF_DCP_CSCXSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
#define BP_DCP_CSCXSCALE_INT        24
#define BM_DCP_CSCXSCALE_INT        0x3000000
#define BF_DCP_CSCXSCALE_INT(v)     (((v) << 24) & 0x3000000)
#define BP_DCP_CSCXSCALE_FRAC       12
#define BM_DCP_CSCXSCALE_FRAC       0xfff000
#define BF_DCP_CSCXSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
#define BP_DCP_CSCXSCALE_WIDTH      0
#define BM_DCP_CSCXSCALE_WIDTH      0xfff
#define BF_DCP_CSCXSCALE_WIDTH(v)   (((v) << 0) & 0xfff)

/**
 * Register: HW_DCP_CSCYSCALE
 * Address: 0x3f0
 * SCT: no
*/
#define HW_DCP_CSCYSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0))
#define BP_DCP_CSCYSCALE_RSVD1      26
#define BM_DCP_CSCYSCALE_RSVD1      0xfc000000
#define BF_DCP_CSCYSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
#define BP_DCP_CSCYSCALE_INT        24
#define BM_DCP_CSCYSCALE_INT        0x3000000
#define BF_DCP_CSCYSCALE_INT(v)     (((v) << 24) & 0x3000000)
#define BP_DCP_CSCYSCALE_FRAC       12
#define BM_DCP_CSCYSCALE_FRAC       0xfff000
#define BF_DCP_CSCYSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
#define BP_DCP_CSCYSCALE_HEIGHT     0
#define BM_DCP_CSCYSCALE_HEIGHT     0xfff
#define BF_DCP_CSCYSCALE_HEIGHT(v)  (((v) << 0) & 0xfff)

/**
 * Register: HW_DCP_DBGSELECT
 * Address: 0x400
 * SCT: no
*/
#define HW_DCP_DBGSELECT                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400))
#define BP_DCP_DBGSELECT_RSVD           8
#define BM_DCP_DBGSELECT_RSVD           0xffffff00
#define BF_DCP_DBGSELECT_RSVD(v)        (((v) << 8) & 0xffffff00)
#define BP_DCP_DBGSELECT_INDEX          0
#define BM_DCP_DBGSELECT_INDEX          0xff
#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
#define BF_DCP_DBGSELECT_INDEX(v)       (((v) << 0) & 0xff)
#define BF_DCP_DBGSELECT_INDEX_V(v)     ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff)

/**
 * Register: HW_DCP_DBGDATA
 * Address: 0x410
 * SCT: no
*/
#define HW_DCP_DBGDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410))
#define BP_DCP_DBGDATA_DATA     0
#define BM_DCP_DBGDATA_DATA     0xffffffff
#define BF_DCP_DBGDATA_DATA(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_DCP_PAGETABLE
 * Address: 0x420
 * SCT: no
*/
#define HW_DCP_PAGETABLE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420))
#define BP_DCP_PAGETABLE_BASE       2
#define BM_DCP_PAGETABLE_BASE       0xfffffffc
#define BF_DCP_PAGETABLE_BASE(v)    (((v) << 2) & 0xfffffffc)
#define BP_DCP_PAGETABLE_FLUSH      1
#define BM_DCP_PAGETABLE_FLUSH      0x2
#define BF_DCP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
#define BP_DCP_PAGETABLE_ENABLE     0
#define BM_DCP_PAGETABLE_ENABLE     0x1
#define BF_DCP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)

/**
 * Register: HW_DCP_VERSION
 * Address: 0x430
 * SCT: no
*/
#define HW_DCP_VERSION          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x430))
#define BP_DCP_VERSION_MAJOR    24
#define BM_DCP_VERSION_MAJOR    0xff000000
#define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
#define BP_DCP_VERSION_MINOR    16
#define BM_DCP_VERSION_MINOR    0xff0000
#define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
#define BP_DCP_VERSION_STEP     0
#define BM_DCP_VERSION_STEP     0xffff
#define BF_DCP_VERSION_STEP(v)  (((v) << 0) & 0xffff)

#endif /* __HEADERGEN__IMX233__DCP__H__ */