path: root/firmware/target/arm/imx233/regs/imx233/regs-pxp.h

/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 2.1.8
 * XML versions: imx233:3.2.0
 *
 * Copyright (C) 2013 by Amaury Pouly
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN__IMX233__PXP__H__
#define __HEADERGEN__IMX233__PXP__H__

#define REGS_PXP_BASE (0x8002a000)

#define REGS_PXP_VERSION "3.2.0"

/**
 * Register: HW_PXP_CTRL
 * Address: 0
 * SCT: yes
*/
#define HW_PXP_CTRL                                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x0))
#define HW_PXP_CTRL_SET                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x4))
#define HW_PXP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x8))
#define HW_PXP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0xc))
#define BP_PXP_CTRL_SFTRST                          31
#define BM_PXP_CTRL_SFTRST                          0x80000000
#define BF_PXP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
#define BP_PXP_CTRL_CLKGATE                         30
#define BM_PXP_CTRL_CLKGATE                         0x40000000
#define BF_PXP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
#define BP_PXP_CTRL_RSVD2                           28
#define BM_PXP_CTRL_RSVD2                           0x30000000
#define BF_PXP_CTRL_RSVD2(v)                        (((v) << 28) & 0x30000000)
#define BP_PXP_CTRL_INTERLACED_OUTPUT               26
#define BM_PXP_CTRL_INTERLACED_OUTPUT               0xc000000
#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE  0x0
#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0       0x1
#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1       0x2
#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED   0x3
#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)            (((v) << 26) & 0xc000000)
#define BF_PXP_CTRL_INTERLACED_OUTPUT_V(v)          ((BV_PXP_CTRL_INTERLACED_OUTPUT__##v << 26) & 0xc000000)
#define BP_PXP_CTRL_INTERLACED_INPUT                24
#define BM_PXP_CTRL_INTERLACED_INPUT                0x3000000
#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE   0x0
#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0        0x2
#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1        0x3
#define BF_PXP_CTRL_INTERLACED_INPUT(v)             (((v) << 24) & 0x3000000)
#define BF_PXP_CTRL_INTERLACED_INPUT_V(v)           ((BV_PXP_CTRL_INTERLACED_INPUT__##v << 24) & 0x3000000)
#define BP_PXP_CTRL_RSVD1                           23
#define BM_PXP_CTRL_RSVD1                           0x800000
#define BF_PXP_CTRL_RSVD1(v)                        (((v) << 23) & 0x800000)
#define BP_PXP_CTRL_ALPHA_OUTPUT                    22
#define BM_PXP_CTRL_ALPHA_OUTPUT                    0x400000
#define BF_PXP_CTRL_ALPHA_OUTPUT(v)                 (((v) << 22) & 0x400000)
#define BP_PXP_CTRL_IN_PLACE                        21
#define BM_PXP_CTRL_IN_PLACE                        0x200000
#define BF_PXP_CTRL_IN_PLACE(v)                     (((v) << 21) & 0x200000)
#define BP_PXP_CTRL_DELTA                           20
#define BM_PXP_CTRL_DELTA                           0x100000
#define BF_PXP_CTRL_DELTA(v)                        (((v) << 20) & 0x100000)
#define BP_PXP_CTRL_CROP                            19
#define BM_PXP_CTRL_CROP                            0x80000
#define BF_PXP_CTRL_CROP(v)                         (((v) << 19) & 0x80000)
#define BP_PXP_CTRL_SCALE                           18
#define BM_PXP_CTRL_SCALE                           0x40000
#define BF_PXP_CTRL_SCALE(v)                        (((v) << 18) & 0x40000)
#define BP_PXP_CTRL_UPSAMPLE                        17
#define BM_PXP_CTRL_UPSAMPLE                        0x20000
#define BF_PXP_CTRL_UPSAMPLE(v)                     (((v) << 17) & 0x20000)
#define BP_PXP_CTRL_SUBSAMPLE                       16
#define BM_PXP_CTRL_SUBSAMPLE                       0x10000
#define BF_PXP_CTRL_SUBSAMPLE(v)                    (((v) << 16) & 0x10000)
#define BP_PXP_CTRL_S0_FORMAT                       12
#define BM_PXP_CTRL_S0_FORMAT                       0xf000
#define BV_PXP_CTRL_S0_FORMAT__RGB888               0x1
#define BV_PXP_CTRL_S0_FORMAT__RGB565               0x4
#define BV_PXP_CTRL_S0_FORMAT__RGB555               0x5
#define BV_PXP_CTRL_S0_FORMAT__YUV422               0x8
#define BV_PXP_CTRL_S0_FORMAT__YUV420               0x9
#define BF_PXP_CTRL_S0_FORMAT(v)                    (((v) << 12) & 0xf000)
#define BF_PXP_CTRL_S0_FORMAT_V(v)                  ((BV_PXP_CTRL_S0_FORMAT__##v << 12) & 0xf000)
#define BP_PXP_CTRL_VFLIP                           11
#define BM_PXP_CTRL_VFLIP                           0x800
#define BF_PXP_CTRL_VFLIP(v)                        (((v) << 11) & 0x800)
#define BP_PXP_CTRL_HFLIP                           10
#define BM_PXP_CTRL_HFLIP                           0x400
#define BF_PXP_CTRL_HFLIP(v)                        (((v) << 10) & 0x400)
#define BP_PXP_CTRL_ROTATE                          8
#define BM_PXP_CTRL_ROTATE                          0x300
#define BV_PXP_CTRL_ROTATE__ROT_0                   0x0
#define BV_PXP_CTRL_ROTATE__ROT_90                  0x1
#define BV_PXP_CTRL_ROTATE__ROT_180                 0x2
#define BV_PXP_CTRL_ROTATE__ROT_270                 0x3
#define BF_PXP_CTRL_ROTATE(v)                       (((v) << 8) & 0x300)
#define BF_PXP_CTRL_ROTATE_V(v)                     ((BV_PXP_CTRL_ROTATE__##v << 8) & 0x300)
#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT               4
#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT               0xf0
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888     0x0
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888       0x1
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P      0x2
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555     0x3
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565       0x4
#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555       0x5
#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v)            (((v) << 4) & 0xf0)
#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT_V(v)          ((BV_PXP_CTRL_OUTPUT_RGB_FORMAT__##v << 4) & 0xf0)
#define BP_PXP_CTRL_RSVD0                           3
#define BM_PXP_CTRL_RSVD0                           0x8
#define BF_PXP_CTRL_RSVD0(v)                        (((v) << 3) & 0x8)
#define BP_PXP_CTRL_ENABLE_LCD_HANDSHAKE            2
#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE            0x4
#define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v)         (((v) << 2) & 0x4)
#define BP_PXP_CTRL_IRQ_ENABLE                      1
#define BM_PXP_CTRL_IRQ_ENABLE                      0x2
#define BF_PXP_CTRL_IRQ_ENABLE(v)                   (((v) << 1) & 0x2)
#define BP_PXP_CTRL_ENABLE                          0
#define BM_PXP_CTRL_ENABLE                          0x1
#define BF_PXP_CTRL_ENABLE(v)                       (((v) << 0) & 0x1)

/**
 * Register: HW_PXP_STAT
 * Address: 0x10
 * SCT: yes
*/
#define HW_PXP_STAT                     (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x0))
#define HW_PXP_STAT_SET                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x4))
#define HW_PXP_STAT_CLR                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x8))
#define HW_PXP_STAT_TOG                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0xc))
#define BP_PXP_STAT_BLOCKX              24
#define BM_PXP_STAT_BLOCKX              0xff000000
#define BF_PXP_STAT_BLOCKX(v)           (((v) << 24) & 0xff000000)
#define BP_PXP_STAT_BLOCKY              16
#define BM_PXP_STAT_BLOCKY              0xff0000
#define BF_PXP_STAT_BLOCKY(v)           (((v) << 16) & 0xff0000)
#define BP_PXP_STAT_RSVD2               8
#define BM_PXP_STAT_RSVD2               0xff00
#define BF_PXP_STAT_RSVD2(v)            (((v) << 8) & 0xff00)
#define BP_PXP_STAT_AXI_ERROR_ID        4
#define BM_PXP_STAT_AXI_ERROR_ID        0xf0
#define BF_PXP_STAT_AXI_ERROR_ID(v)     (((v) << 4) & 0xf0)
#define BP_PXP_STAT_RSVD1               3
#define BM_PXP_STAT_RSVD1               0x8
#define BF_PXP_STAT_RSVD1(v)            (((v) << 3) & 0x8)
#define BP_PXP_STAT_AXI_READ_ERROR      2
#define BM_PXP_STAT_AXI_READ_ERROR      0x4
#define BF_PXP_STAT_AXI_READ_ERROR(v)   (((v) << 2) & 0x4)
#define BP_PXP_STAT_AXI_WRITE_ERROR     1
#define BM_PXP_STAT_AXI_WRITE_ERROR     0x2
#define BF_PXP_STAT_AXI_WRITE_ERROR(v)  (((v) << 1) & 0x2)
#define BP_PXP_STAT_IRQ                 0
#define BM_PXP_STAT_IRQ                 0x1
#define BF_PXP_STAT_IRQ(v)              (((v) << 0) & 0x1)

/**
 * Register: HW_PXP_RGBBUF
 * Address: 0x20
 * SCT: no
*/
#define HW_PXP_RGBBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x20))
#define BP_PXP_RGBBUF_ADDR      0
#define BM_PXP_RGBBUF_ADDR      0xffffffff
#define BF_PXP_RGBBUF_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_RGBBUF2
 * Address: 0x30
 * SCT: no
*/
#define HW_PXP_RGBBUF2          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x30))
#define BP_PXP_RGBBUF2_ADDR     0
#define BM_PXP_RGBBUF2_ADDR     0xffffffff
#define BF_PXP_RGBBUF2_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_RGBSIZE
 * Address: 0x40
 * SCT: no
*/
#define HW_PXP_RGBSIZE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x40))
#define BP_PXP_RGBSIZE_ALPHA        24
#define BM_PXP_RGBSIZE_ALPHA        0xff000000
#define BF_PXP_RGBSIZE_ALPHA(v)     (((v) << 24) & 0xff000000)
#define BP_PXP_RGBSIZE_WIDTH        12
#define BM_PXP_RGBSIZE_WIDTH        0xfff000
#define BF_PXP_RGBSIZE_WIDTH(v)     (((v) << 12) & 0xfff000)
#define BP_PXP_RGBSIZE_HEIGHT       0
#define BM_PXP_RGBSIZE_HEIGHT       0xfff
#define BF_PXP_RGBSIZE_HEIGHT(v)    (((v) << 0) & 0xfff)

/**
 * Register: HW_PXP_S0BUF
 * Address: 0x50
 * SCT: no
*/
#define HW_PXP_S0BUF            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x50))
#define BP_PXP_S0BUF_ADDR       0
#define BM_PXP_S0BUF_ADDR       0xffffffff
#define BF_PXP_S0BUF_ADDR(v)    (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_S0UBUF
 * Address: 0x60
 * SCT: no
*/
#define HW_PXP_S0UBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x60))
#define BP_PXP_S0UBUF_ADDR      0
#define BM_PXP_S0UBUF_ADDR      0xffffffff
#define BF_PXP_S0UBUF_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_S0VBUF
 * Address: 0x70
 * SCT: no
*/
#define HW_PXP_S0VBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x70))
#define BP_PXP_S0VBUF_ADDR      0
#define BM_PXP_S0VBUF_ADDR      0xffffffff
#define BF_PXP_S0VBUF_ADDR(v)   (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_S0PARAM
 * Address: 0x80
 * SCT: no
*/
#define HW_PXP_S0PARAM              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x80))
#define BP_PXP_S0PARAM_XBASE        24
#define BM_PXP_S0PARAM_XBASE        0xff000000
#define BF_PXP_S0PARAM_XBASE(v)     (((v) << 24) & 0xff000000)
#define BP_PXP_S0PARAM_YBASE        16
#define BM_PXP_S0PARAM_YBASE        0xff0000
#define BF_PXP_S0PARAM_YBASE(v)     (((v) << 16) & 0xff0000)
#define BP_PXP_S0PARAM_WIDTH        8
#define BM_PXP_S0PARAM_WIDTH        0xff00
#define BF_PXP_S0PARAM_WIDTH(v)     (((v) << 8) & 0xff00)
#define BP_PXP_S0PARAM_HEIGHT       0
#define BM_PXP_S0PARAM_HEIGHT       0xff
#define BF_PXP_S0PARAM_HEIGHT(v)    (((v) << 0) & 0xff)

/**
 * Register: HW_PXP_S0BACKGROUND
 * Address: 0x90
 * SCT: no
*/
#define HW_PXP_S0BACKGROUND             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x90))
#define BP_PXP_S0BACKGROUND_COLOR       0
#define BM_PXP_S0BACKGROUND_COLOR       0xffffffff
#define BF_PXP_S0BACKGROUND_COLOR(v)    (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_S0CROP
 * Address: 0xa0
 * SCT: no
*/
#define HW_PXP_S0CROP           (*(volatile unsigned long *)(REGS_PXP_BASE + 0xa0))
#define BP_PXP_S0CROP_XBASE     24
#define BM_PXP_S0CROP_XBASE     0xff000000
#define BF_PXP_S0CROP_XBASE(v)  (((v) << 24) & 0xff000000)
#define BP_PXP_S0CROP_YBASE     16
#define BM_PXP_S0CROP_YBASE     0xff0000
#define BF_PXP_S0CROP_YBASE(v)  (((v) << 16) & 0xff0000)
#define BP_PXP_S0CROP_WIDTH     8
#define BM_PXP_S0CROP_WIDTH     0xff00
#define BF_PXP_S0CROP_WIDTH(v)  (((v) << 8) & 0xff00)
#define BP_PXP_S0CROP_HEIGHT    0
#define BM_PXP_S0CROP_HEIGHT    0xff
#define BF_PXP_S0CROP_HEIGHT(v) (((v) << 0) & 0xff)

/**
 * Register: HW_PXP_S0SCALE
 * Address: 0xb0
 * SCT: no
*/
#define HW_PXP_S0SCALE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0xb0))
#define BP_PXP_S0SCALE_RSVD2        30
#define BM_PXP_S0SCALE_RSVD2        0xc0000000
#define BF_PXP_S0SCALE_RSVD2(v)     (((v) << 30) & 0xc0000000)
#define BP_PXP_S0SCALE_YSCALE       16
#define BM_PXP_S0SCALE_YSCALE       0x3fff0000
#define BF_PXP_S0SCALE_YSCALE(v)    (((v) << 16) & 0x3fff0000)
#define BP_PXP_S0SCALE_RSVD1        14
#define BM_PXP_S0SCALE_RSVD1        0xc000
#define BF_PXP_S0SCALE_RSVD1(v)     (((v) << 14) & 0xc000)
#define BP_PXP_S0SCALE_XSCALE       0
#define BM_PXP_S0SCALE_XSCALE       0x3fff
#define BF_PXP_S0SCALE_XSCALE(v)    (((v) << 0) & 0x3fff)

/**
 * Register: HW_PXP_S0OFFSET
 * Address: 0xc0
 * SCT: no
*/
#define HW_PXP_S0OFFSET             (*(volatile unsigned long *)(REGS_PXP_BASE + 0xc0))
#define BP_PXP_S0OFFSET_RSVD2       28
#define BM_PXP_S0OFFSET_RSVD2       0xf0000000
#define BF_PXP_S0OFFSET_RSVD2(v)    (((v) << 28) & 0xf0000000)
#define BP_PXP_S0OFFSET_YOFFSET     16
#define BM_PXP_S0OFFSET_YOFFSET     0xfff0000
#define BF_PXP_S0OFFSET_YOFFSET(v)  (((v) << 16) & 0xfff0000)
#define BP_PXP_S0OFFSET_RSVD1       12
#define BM_PXP_S0OFFSET_RSVD1       0xf000
#define BF_PXP_S0OFFSET_RSVD1(v)    (((v) << 12) & 0xf000)
#define BP_PXP_S0OFFSET_XOFFSET     0
#define BM_PXP_S0OFFSET_XOFFSET     0xfff
#define BF_PXP_S0OFFSET_XOFFSET(v)  (((v) << 0) & 0xfff)

/**
 * Register: HW_PXP_CSCCOEFF0
 * Address: 0xd0
 * SCT: no
*/
#define HW_PXP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_PXP_BASE + 0xd0))
#define BP_PXP_CSCCOEFF0_YCBCR_MODE     31
#define BM_PXP_CSCCOEFF0_YCBCR_MODE     0x80000000
#define BF_PXP_CSCCOEFF0_YCBCR_MODE(v)  (((v) << 31) & 0x80000000)
#define BP_PXP_CSCCOEFF0_RSVD1          29
#define BM_PXP_CSCCOEFF0_RSVD1          0x60000000
#define BF_PXP_CSCCOEFF0_RSVD1(v)       (((v) << 29) & 0x60000000)
#define BP_PXP_CSCCOEFF0_C0             18
#define BM_PXP_CSCCOEFF0_C0             0x1ffc0000
#define BF_PXP_CSCCOEFF0_C0(v)          (((v) << 18) & 0x1ffc0000)
#define BP_PXP_CSCCOEFF0_UV_OFFSET      9
#define BM_PXP_CSCCOEFF0_UV_OFFSET      0x3fe00
#define BF_PXP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 9) & 0x3fe00)
#define BP_PXP_CSCCOEFF0_Y_OFFSET       0
#define BM_PXP_CSCCOEFF0_Y_OFFSET       0x1ff
#define BF_PXP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0x1ff)

/**
 * Register: HW_PXP_CSCCOEFF1
 * Address: 0xe0
 * SCT: no
*/
#define HW_PXP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xe0))
#define BP_PXP_CSCCOEFF1_RSVD1      27
#define BM_PXP_CSCCOEFF1_RSVD1      0xf8000000
#define BF_PXP_CSCCOEFF1_RSVD1(v)   (((v) << 27) & 0xf8000000)
#define BP_PXP_CSCCOEFF1_C1         16
#define BM_PXP_CSCCOEFF1_C1         0x7ff0000
#define BF_PXP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x7ff0000)
#define BP_PXP_CSCCOEFF1_RSVD0      11
#define BM_PXP_CSCCOEFF1_RSVD0      0xf800
#define BF_PXP_CSCCOEFF1_RSVD0(v)   (((v) << 11) & 0xf800)
#define BP_PXP_CSCCOEFF1_C4         0
#define BM_PXP_CSCCOEFF1_C4         0x7ff
#define BF_PXP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x7ff)

/**
 * Register: HW_PXP_CSCCOEFF2
 * Address: 0xf0
 * SCT: no
*/
#define HW_PXP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xf0))
#define BP_PXP_CSCCOEFF2_RSVD1      27
#define BM_PXP_CSCCOEFF2_RSVD1      0xf8000000
#define BF_PXP_CSCCOEFF2_RSVD1(v)   (((v) << 27) & 0xf8000000)
#define BP_PXP_CSCCOEFF2_C2         16
#define BM_PXP_CSCCOEFF2_C2         0x7ff0000
#define BF_PXP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x7ff0000)
#define BP_PXP_CSCCOEFF2_RSVD0      11
#define BM_PXP_CSCCOEFF2_RSVD0      0xf800
#define BF_PXP_CSCCOEFF2_RSVD0(v)   (((v) << 11) & 0xf800)
#define BP_PXP_CSCCOEFF2_C3         0
#define BM_PXP_CSCCOEFF2_C3         0x7ff
#define BF_PXP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x7ff)

/**
 * Register: HW_PXP_NEXT
 * Address: 0x100
 * SCT: yes
*/
#define HW_PXP_NEXT             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x0))
#define HW_PXP_NEXT_SET         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x4))
#define HW_PXP_NEXT_CLR         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x8))
#define HW_PXP_NEXT_TOG         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0xc))
#define BP_PXP_NEXT_POINTER     2
#define BM_PXP_NEXT_POINTER     0xfffffffc
#define BF_PXP_NEXT_POINTER(v)  (((v) << 2) & 0xfffffffc)
#define BP_PXP_NEXT_RSVD        1
#define BM_PXP_NEXT_RSVD        0x2
#define BF_PXP_NEXT_RSVD(v)     (((v) << 1) & 0x2)
#define BP_PXP_NEXT_ENABLED     0
#define BM_PXP_NEXT_ENABLED     0x1
#define BF_PXP_NEXT_ENABLED(v)  (((v) << 0) & 0x1)

/**
 * Register: HW_PXP_PAGETABLE
 * Address: 0x170
 * SCT: no
*/
#define HW_PXP_PAGETABLE            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x170))
#define BP_PXP_PAGETABLE_BASE       14
#define BM_PXP_PAGETABLE_BASE       0xffffc000
#define BF_PXP_PAGETABLE_BASE(v)    (((v) << 14) & 0xffffc000)
#define BP_PXP_PAGETABLE_RSVD1      2
#define BM_PXP_PAGETABLE_RSVD1      0x3ffc
#define BF_PXP_PAGETABLE_RSVD1(v)   (((v) << 2) & 0x3ffc)
#define BP_PXP_PAGETABLE_FLUSH      1
#define BM_PXP_PAGETABLE_FLUSH      0x2
#define BF_PXP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
#define BP_PXP_PAGETABLE_ENABLE     0
#define BM_PXP_PAGETABLE_ENABLE     0x1
#define BF_PXP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)

/**
 * Register: HW_PXP_S0COLORKEYLOW
 * Address: 0x180
 * SCT: no
*/
#define HW_PXP_S0COLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x180))
#define BP_PXP_S0COLORKEYLOW_RSVD1      24
#define BM_PXP_S0COLORKEYLOW_RSVD1      0xff000000
#define BF_PXP_S0COLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
#define BP_PXP_S0COLORKEYLOW_PIXEL      0
#define BM_PXP_S0COLORKEYLOW_PIXEL      0xffffff
#define BF_PXP_S0COLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)

/**
 * Register: HW_PXP_S0COLORKEYHIGH
 * Address: 0x190
 * SCT: no
*/
#define HW_PXP_S0COLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x190))
#define BP_PXP_S0COLORKEYHIGH_RSVD1     24
#define BM_PXP_S0COLORKEYHIGH_RSVD1     0xff000000
#define BF_PXP_S0COLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
#define BP_PXP_S0COLORKEYHIGH_PIXEL     0
#define BM_PXP_S0COLORKEYHIGH_PIXEL     0xffffff
#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)

/**
 * Register: HW_PXP_OLCOLORKEYLOW
 * Address: 0x1a0
 * SCT: no
*/
#define HW_PXP_OLCOLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1a0))
#define BP_PXP_OLCOLORKEYLOW_RSVD1      24
#define BM_PXP_OLCOLORKEYLOW_RSVD1      0xff000000
#define BF_PXP_OLCOLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
#define BP_PXP_OLCOLORKEYLOW_PIXEL      0
#define BM_PXP_OLCOLORKEYLOW_PIXEL      0xffffff
#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)

/**
 * Register: HW_PXP_OLCOLORKEYHIGH
 * Address: 0x1b0
 * SCT: no
*/
#define HW_PXP_OLCOLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1b0))
#define BP_PXP_OLCOLORKEYHIGH_RSVD1     24
#define BM_PXP_OLCOLORKEYHIGH_RSVD1     0xff000000
#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
#define BP_PXP_OLCOLORKEYHIGH_PIXEL     0
#define BM_PXP_OLCOLORKEYHIGH_PIXEL     0xffffff
#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)

/**
 * Register: HW_PXP_DEBUGCTRL
 * Address: 0x1d0
 * SCT: no
*/
#define HW_PXP_DEBUGCTRL                    (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1d0))
#define BP_PXP_DEBUGCTRL_RSVD               9
#define BM_PXP_DEBUGCTRL_RSVD               0xfffffe00
#define BF_PXP_DEBUGCTRL_RSVD(v)            (((v) << 9) & 0xfffffe00)
#define BP_PXP_DEBUGCTRL_RESET_TLB_STATS    8
#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS    0x100
#define BF_PXP_DEBUGCTRL_RESET_TLB_STATS(v) (((v) << 8) & 0x100)
#define BP_PXP_DEBUGCTRL_SELECT             0
#define BM_PXP_DEBUGCTRL_SELECT             0xff
#define BV_PXP_DEBUGCTRL_SELECT__NONE       0x0
#define BV_PXP_DEBUGCTRL_SELECT__CTRL       0x1
#define BV_PXP_DEBUGCTRL_SELECT__S0REGS     0x2
#define BV_PXP_DEBUGCTRL_SELECT__S0BAX      0x3
#define BV_PXP_DEBUGCTRL_SELECT__S0BAY      0x4
#define BV_PXP_DEBUGCTRL_SELECT__PXBUF      0x5
#define BV_PXP_DEBUGCTRL_SELECT__ROTATION   0x6
#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0    0x7
#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1    0x8
#define BF_PXP_DEBUGCTRL_SELECT(v)          (((v) << 0) & 0xff)
#define BF_PXP_DEBUGCTRL_SELECT_V(v)        ((BV_PXP_DEBUGCTRL_SELECT__##v << 0) & 0xff)

/**
 * Register: HW_PXP_DEBUG
 * Address: 0x1e0
 * SCT: no
*/
#define HW_PXP_DEBUG            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1e0))
#define BP_PXP_DEBUG_DATA       0
#define BM_PXP_DEBUG_DATA       0xffffffff
#define BF_PXP_DEBUG_DATA(v)    (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_VERSION
 * Address: 0x1f0
 * SCT: no
*/
#define HW_PXP_VERSION          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1f0))
#define BP_PXP_VERSION_MAJOR    24
#define BM_PXP_VERSION_MAJOR    0xff000000
#define BF_PXP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
#define BP_PXP_VERSION_MINOR    16
#define BM_PXP_VERSION_MINOR    0xff0000
#define BF_PXP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
#define BP_PXP_VERSION_STEP     0
#define BM_PXP_VERSION_STEP     0xffff
#define BF_PXP_VERSION_STEP(v)  (((v) << 0) & 0xffff)

/**
 * Register: HW_PXP_OLn
 * Address: 0x200+n*0x40
 * SCT: no
*/
#define HW_PXP_OLn(n)       (*(volatile unsigned long *)(REGS_PXP_BASE + 0x200+(n)*0x40))
#define BP_PXP_OLn_ADDR     0
#define BM_PXP_OLn_ADDR     0xffffffff
#define BF_PXP_OLn_ADDR(v)  (((v) << 0) & 0xffffffff)

/**
 * Register: HW_PXP_OLnSIZE
 * Address: 0x210+n*0x40
 * SCT: no
*/
#define HW_PXP_OLnSIZE(n)           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x210+(n)*0x40))
#define BP_PXP_OLnSIZE_XBASE        24
#define BM_PXP_OLnSIZE_XBASE        0xff000000
#define BF_PXP_OLnSIZE_XBASE(v)     (((v) << 24) & 0xff000000)
#define BP_PXP_OLnSIZE_YBASE        16
#define BM_PXP_OLnSIZE_YBASE        0xff0000
#define BF_PXP_OLnSIZE_YBASE(v)     (((v) << 16) & 0xff0000)
#define BP_PXP_OLnSIZE_WIDTH        8
#define BM_PXP_OLnSIZE_WIDTH        0xff00
#define BF_PXP_OLnSIZE_WIDTH(v)     (((v) << 8) & 0xff00)
#define BP_PXP_OLnSIZE_HEIGHT       0
#define BM_PXP_OLnSIZE_HEIGHT       0xff
#define BF_PXP_OLnSIZE_HEIGHT(v)    (((v) << 0) & 0xff)

/**
 * Register: HW_PXP_OLnPARAM
 * Address: 0x220+n*0x40
 * SCT: no
*/
#define HW_PXP_OLnPARAM(n)                      (*(volatile unsigned long *)(REGS_PXP_BASE + 0x220+(n)*0x40))
#define BP_PXP_OLnPARAM_RSVD1                   20
#define BM_PXP_OLnPARAM_RSVD1                   0xfff00000
#define BF_PXP_OLnPARAM_RSVD1(v)                (((v) << 20) & 0xfff00000)
#define BP_PXP_OLnPARAM_ROP                     16
#define BM_PXP_OLnPARAM_ROP                     0xf0000
#define BV_PXP_OLnPARAM_ROP__MASKOL             0x0
#define BV_PXP_OLnPARAM_ROP__MASKNOTOL          0x1
#define BV_PXP_OLnPARAM_ROP__MASKOLNOT          0x2
#define BV_PXP_OLnPARAM_ROP__MERGEOL            0x3
#define BV_PXP_OLnPARAM_ROP__MERGENOTOL         0x4
#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT         0x5
#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL          0x6
#define BV_PXP_OLnPARAM_ROP__NOT                0x7
#define BV_PXP_OLnPARAM_ROP__NOTMASKOL          0x8
#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL         0x9
#define BV_PXP_OLnPARAM_ROP__XOROL              0xa
#define BV_PXP_OLnPARAM_ROP__NOTXOROL           0xb
#define BF_PXP_OLnPARAM_ROP(v)                  (((v) << 16) & 0xf0000)
#define BF_PXP_OLnPARAM_ROP_V(v)                ((BV_PXP_OLnPARAM_ROP__##v << 16) & 0xf0000)
#define BP_PXP_OLnPARAM_ALPHA                   8
#define BM_PXP_OLnPARAM_ALPHA                   0xff00
#define BF_PXP_OLnPARAM_ALPHA(v)                (((v) << 8) & 0xff00)
#define BP_PXP_OLnPARAM_FORMAT                  4
#define BM_PXP_OLnPARAM_FORMAT                  0xf0
#define BV_PXP_OLnPARAM_FORMAT__ARGB8888        0x0
#define BV_PXP_OLnPARAM_FORMAT__RGB888          0x1
#define BV_PXP_OLnPARAM_FORMAT__ARGB1555        0x3
#define BV_PXP_OLnPARAM_FORMAT__RGB565          0x4
#define BV_PXP_OLnPARAM_FORMAT__RGB555          0x5
#define BF_PXP_OLnPARAM_FORMAT(v)               (((v) << 4) & 0xf0)
#define BF_PXP_OLnPARAM_FORMAT_V(v)             ((BV_PXP_OLnPARAM_FORMAT__##v << 4) & 0xf0)
#define BP_PXP_OLnPARAM_ENABLE_COLORKEY         3
#define BM_PXP_OLnPARAM_ENABLE_COLORKEY         0x8
#define BF_PXP_OLnPARAM_ENABLE_COLORKEY(v)      (((v) << 3) & 0x8)
#define BP_PXP_OLnPARAM_ALPHA_CNTL              1
#define BM_PXP_OLnPARAM_ALPHA_CNTL              0x6
#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded    0x0
#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override    0x1
#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply    0x2
#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs        0x3
#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)           (((v) << 1) & 0x6)
#define BF_PXP_OLnPARAM_ALPHA_CNTL_V(v)         ((BV_PXP_OLnPARAM_ALPHA_CNTL__##v << 1) & 0x6)
#define BP_PXP_OLnPARAM_ENABLE                  0
#define BM_PXP_OLnPARAM_ENABLE                  0x1
#define BF_PXP_OLnPARAM_ENABLE(v)               (((v) << 0) & 0x1)

/**
 * Register: HW_PXP_OLnPARAM2
 * Address: 0x230+n*0x40
 * SCT: no
*/
#define HW_PXP_OLnPARAM2(n)         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x230+(n)*0x40))
#define BP_PXP_OLnPARAM2_RSVD       0
#define BM_PXP_OLnPARAM2_RSVD       0xffffffff
#define BF_PXP_OLnPARAM2_RSVD(v)    (((v) << 0) & 0xffffffff)

#endif /* __HEADERGEN__IMX233__PXP__H__ */