summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/imx233/regs/imx233/regs-sydma.h
blob: ec0a4bc9592937c1b2a929424c8993f1c17a023c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 2.1.7
 * XML versions: imx233:3.2.0
 *
 * Copyright (C) 2013 by Amaury Pouly
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN__IMX233__SYDMA__H__
#define __HEADERGEN__IMX233__SYDMA__H__

#define REGS_SYDMA_BASE (0x80026000)

#define REGS_SYDMA_VERSION "3.2.0"

/**
 * Register: HW_SYDMA_CTRL
 * Address: 0
 * SCT: yes
*/
#define HW_SYDMA_CTRL                           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x0))
#define HW_SYDMA_CTRL_SET                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x4))
#define HW_SYDMA_CTRL_CLR                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x8))
#define HW_SYDMA_CTRL_TOG                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0xc))
#define BP_SYDMA_CTRL_SFTRST                    31
#define BM_SYDMA_CTRL_SFTRST                    0x80000000
#define BV_SYDMA_CTRL_SFTRST__RUN               0x0
#define BV_SYDMA_CTRL_SFTRST__RESET             0x1
#define BF_SYDMA_CTRL_SFTRST(v)                 (((v) << 31) & 0x80000000)
#define BF_SYDMA_CTRL_SFTRST_V(v)               ((BV_SYDMA_CTRL_SFTRST__##v << 31) & 0x80000000)
#define BP_SYDMA_CTRL_CLKGATE                   30
#define BM_SYDMA_CTRL_CLKGATE                   0x40000000
#define BV_SYDMA_CTRL_CLKGATE__RUN              0x0
#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS          0x1
#define BF_SYDMA_CTRL_CLKGATE(v)                (((v) << 30) & 0x40000000)
#define BF_SYDMA_CTRL_CLKGATE_V(v)              ((BV_SYDMA_CTRL_CLKGATE__##v << 30) & 0x40000000)
#define BP_SYDMA_CTRL_RSVD1                     10
#define BM_SYDMA_CTRL_RSVD1                     0x3ffffc00
#define BF_SYDMA_CTRL_RSVD1(v)                  (((v) << 10) & 0x3ffffc00)
#define BP_SYDMA_CTRL_COMPLETE_IRQ_EN           9
#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN           0x200
#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0
#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED  0x1
#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v)        (((v) << 9) & 0x200)
#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v)      ((BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##v << 9) & 0x200)
#define BP_SYDMA_CTRL_RSVD0                     3
#define BM_SYDMA_CTRL_RSVD0                     0x1f8
#define BF_SYDMA_CTRL_RSVD0(v)                  (((v) << 3) & 0x1f8)
#define BP_SYDMA_CTRL_ERROR_IRQ                 2
#define BM_SYDMA_CTRL_ERROR_IRQ                 0x4
#define BF_SYDMA_CTRL_ERROR_IRQ(v)              (((v) << 2) & 0x4)
#define BP_SYDMA_CTRL_COMPLETE_IRQ              1
#define BM_SYDMA_CTRL_COMPLETE_IRQ              0x2
#define BF_SYDMA_CTRL_COMPLETE_IRQ(v)           (((v) << 1) & 0x2)
#define BP_SYDMA_CTRL_RUN                       0
#define BM_SYDMA_CTRL_RUN                       0x1
#define BV_SYDMA_CTRL_RUN__HALT                 0x0
#define BV_SYDMA_CTRL_RUN__RUN                  0x1
#define BF_SYDMA_CTRL_RUN(v)                    (((v) << 0) & 0x1)
#define BF_SYDMA_CTRL_RUN_V(v)                  ((BV_SYDMA_CTRL_RUN__##v << 0) & 0x1)

/**
 * Register: HW_SYDMA_RADDR
 * Address: 0x10
 * SCT: no
*/
#define HW_SYDMA_RADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x10))
#define BP_SYDMA_RADDR_RSRC_ADDR    0
#define BM_SYDMA_RADDR_RSRC_ADDR    0xffffffff
#define BF_SYDMA_RADDR_RSRC_ADDR(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_WADDR
 * Address: 0x20
 * SCT: no
*/
#define HW_SYDMA_WADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x20))
#define BP_SYDMA_WADDR_WSRC_ADDR    0
#define BM_SYDMA_WADDR_WSRC_ADDR    0xffffffff
#define BF_SYDMA_WADDR_WSRC_ADDR(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_XFER_COUNT
 * Address: 0x30
 * SCT: no
*/
#define HW_SYDMA_XFER_COUNT         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x30))
#define BP_SYDMA_XFER_COUNT_SIZE    0
#define BM_SYDMA_XFER_COUNT_SIZE    0xffffffff
#define BF_SYDMA_XFER_COUNT_SIZE(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_BURST
 * Address: 0x40
 * SCT: no
*/
#define HW_SYDMA_BURST              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x40))
#define BP_SYDMA_BURST_RSVD0        4
#define BM_SYDMA_BURST_RSVD0        0xfffffff0
#define BF_SYDMA_BURST_RSVD0(v)     (((v) << 4) & 0xfffffff0)
#define BP_SYDMA_BURST_WLEN         2
#define BM_SYDMA_BURST_WLEN         0xc
#define BV_SYDMA_BURST_WLEN__1      0x0
#define BV_SYDMA_BURST_WLEN__2      0x1
#define BV_SYDMA_BURST_WLEN__4      0x2
#define BV_SYDMA_BURST_WLEN__8      0x3
#define BF_SYDMA_BURST_WLEN(v)      (((v) << 2) & 0xc)
#define BF_SYDMA_BURST_WLEN_V(v)    ((BV_SYDMA_BURST_WLEN__##v << 2) & 0xc)
#define BP_SYDMA_BURST_RLEN         0
#define BM_SYDMA_BURST_RLEN         0x3
#define BV_SYDMA_BURST_RLEN__1      0x0
#define BV_SYDMA_BURST_RLEN__2      0x1
#define BV_SYDMA_BURST_RLEN__4      0x2
#define BV_SYDMA_BURST_RLEN__8      0x3
#define BF_SYDMA_BURST_RLEN(v)      (((v) << 0) & 0x3)
#define BF_SYDMA_BURST_RLEN_V(v)    ((BV_SYDMA_BURST_RLEN__##v << 0) & 0x3)

/**
 * Register: HW_SYDMA_DACK
 * Address: 0x50
 * SCT: no
*/
#define HW_SYDMA_DACK           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x50))
#define BP_SYDMA_DACK_RSVD0     8
#define BM_SYDMA_DACK_RSVD0     0xffffff00
#define BF_SYDMA_DACK_RSVD0(v)  (((v) << 8) & 0xffffff00)
#define BP_SYDMA_DACK_WDELAY    4
#define BM_SYDMA_DACK_WDELAY    0xf0
#define BF_SYDMA_DACK_WDELAY(v) (((v) << 4) & 0xf0)
#define BP_SYDMA_DACK_RDELAY    0
#define BM_SYDMA_DACK_RDELAY    0xf
#define BF_SYDMA_DACK_RDELAY(v) (((v) << 0) & 0xf)

/**
 * Register: HW_SYDMA_DEBUG0
 * Address: 0x100
 * SCT: no
*/
#define HW_SYDMA_DEBUG0         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x100))
#define BP_SYDMA_DEBUG0_DATA    0
#define BM_SYDMA_DEBUG0_DATA    0xffffffff
#define BF_SYDMA_DEBUG0_DATA(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_DEBUG1
 * Address: 0x110
 * SCT: no
*/
#define HW_SYDMA_DEBUG1         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x110))
#define BP_SYDMA_DEBUG1_DATA    0
#define BM_SYDMA_DEBUG1_DATA    0xffffffff
#define BF_SYDMA_DEBUG1_DATA(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_DEBUG2
 * Address: 0x120
 * SCT: no
*/
#define HW_SYDMA_DEBUG2         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x120))
#define BP_SYDMA_DEBUG2_DATA    0
#define BM_SYDMA_DEBUG2_DATA    0xffffffff
#define BF_SYDMA_DEBUG2_DATA(v) (((v) << 0) & 0xffffffff)

/**
 * Register: HW_SYDMA_VERSION
 * Address: 0x130
 * SCT: no
*/
#define HW_SYDMA_VERSION            (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x130))
#define BP_SYDMA_VERSION_MAJOR      24
#define BM_SYDMA_VERSION_MAJOR      0xff000000
#define BF_SYDMA_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
#define BP_SYDMA_VERSION_MINOR      16
#define BM_SYDMA_VERSION_MINOR      0xff0000
#define BF_SYDMA_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
#define BP_SYDMA_VERSION_STEP       0
#define BM_SYDMA_VERSION_STEP       0xffff
#define BF_SYDMA_VERSION_STEP(v)    (((v) << 0) & 0xffff)

#endif /* __HEADERGEN__IMX233__SYDMA__H__ */