blob: 716eccfba7e3fd349165a4921297f7a95eae5567 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
|
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 2.1.8
* XML versions: stmp3700:3.2.0
*
* Copyright (C) 2013 by Amaury Pouly
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN__STMP3700__DRI__H__
#define __HEADERGEN__STMP3700__DRI__H__
#define REGS_DRI_BASE (0x80074000)
#define REGS_DRI_VERSION "3.2.0"
/**
* Register: HW_DRI_CTRL
* Address: 0
* SCT: yes
*/
#define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
#define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
#define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
#define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
#define BP_DRI_CTRL_SFTRST 31
#define BM_DRI_CTRL_SFTRST 0x80000000
#define BV_DRI_CTRL_SFTRST__RUN 0x0
#define BV_DRI_CTRL_SFTRST__RESET 0x1
#define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
#define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
#define BP_DRI_CTRL_CLKGATE 30
#define BM_DRI_CTRL_CLKGATE 0x40000000
#define BV_DRI_CTRL_CLKGATE__RUN 0x0
#define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1
#define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
#define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
#define BP_DRI_CTRL_ENABLE_INPUTS 29
#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0
#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1
#define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000)
#define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26
#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000
#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0
#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1
#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000)
#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25
#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000
#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0
#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1
#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000)
#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
#define BP_DRI_CTRL_DMA_DELAY_COUNT 16
#define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000
#define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000)
#define BP_DRI_CTRL_REACQUIRE_PHASE 15
#define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000
#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0
#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1
#define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000)
#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
#define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11
#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800
#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0
#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1
#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800)
#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400
#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0
#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1
#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400)
#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
#define BP_DRI_CTRL_ATTENTION_IRQ_EN 9
#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200
#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0
#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1
#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200)
#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
#define BP_DRI_CTRL_OVERFLOW_IRQ 3
#define BM_DRI_CTRL_OVERFLOW_IRQ 0x8
#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0
#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1
#define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8)
#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4
#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0
#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1
#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4)
#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
#define BP_DRI_CTRL_ATTENTION_IRQ 1
#define BM_DRI_CTRL_ATTENTION_IRQ 0x2
#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0
#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1
#define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2)
#define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
#define BP_DRI_CTRL_RUN 0
#define BM_DRI_CTRL_RUN 0x1
#define BV_DRI_CTRL_RUN__HALT 0x0
#define BV_DRI_CTRL_RUN__RUN 0x1
#define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1)
#define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
/**
* Register: HW_DRI_TIMING
* Address: 0x10
* SCT: no
*/
#define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
#define BP_DRI_TIMING_PILOT_REP_RATE 16
#define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000
#define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000)
#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff
#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
/**
* Register: HW_DRI_STAT
* Address: 0x20
* SCT: no
*/
#define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
#define BP_DRI_STAT_DRI_PRESENT 31
#define BM_DRI_STAT_DRI_PRESENT 0x80000000
#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0
#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1
#define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000)
#define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
#define BP_DRI_STAT_PILOT_PHASE 16
#define BM_DRI_STAT_PILOT_PHASE 0xf0000
#define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000)
#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3
#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8
#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1
#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8)
#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2
#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4
#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1
#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4)
#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1
#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2
#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0
#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1
#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2)
#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
/**
* Register: HW_DRI_DATA
* Address: 0x30
* SCT: no
*/
#define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
#define BP_DRI_DATA_DATA 0
#define BM_DRI_DATA_DATA 0xffffffff
#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
/**
* Register: HW_DRI_DEBUG0
* Address: 0x40
* SCT: yes
*/
#define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
#define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
#define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
#define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
#define BP_DRI_DEBUG0_DMAREQ 31
#define BM_DRI_DEBUG0_DMAREQ 0x80000000
#define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000)
#define BP_DRI_DEBUG0_DMACMDKICK 30
#define BM_DRI_DEBUG0_DMACMDKICK 0x40000000
#define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000)
#define BP_DRI_DEBUG0_DRI_CLK_INPUT 29
#define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000
#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000)
#define BP_DRI_DEBUG0_DRI_DATA_INPUT 28
#define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000
#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000)
#define BP_DRI_DEBUG0_TEST_MODE 27
#define BM_DRI_DEBUG0_TEST_MODE 0x8000000
#define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000)
#define BP_DRI_DEBUG0_PILOT_REP_RATE 26
#define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000
#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0
#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1
#define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000)
#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
#define BP_DRI_DEBUG0_SPARE 18
#define BM_DRI_DEBUG0_SPARE 0x3fc0000
#define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000)
#define BP_DRI_DEBUG0_FRAME 0
#define BM_DRI_DEBUG0_FRAME 0x3ffff
#define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff)
/**
* Register: HW_DRI_DEBUG1
* Address: 0x50
* SCT: yes
*/
#define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
#define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
#define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
#define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
#define BP_DRI_DEBUG1_INVERT_PILOT 31
#define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000
#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0
#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1
#define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000)
#define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
#define BP_DRI_DEBUG1_INVERT_ATTENTION 30
#define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000
#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0
#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1
#define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000)
#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
#define BP_DRI_DEBUG1_INVERT_DRI_DATA 29
#define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000
#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0
#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1
#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000)
#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28
#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000
#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0
#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1
#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000)
#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
#define BP_DRI_DEBUG1_REVERSE_FRAME 27
#define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000
#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0
#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1
#define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000)
#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
#define BP_DRI_DEBUG1_SWIZZLED_FRAME 0
#define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff
#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff)
/**
* Register: HW_DRI_VERSION
* Address: 0x60
* SCT: no
*/
#define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
#define BP_DRI_VERSION_MAJOR 24
#define BM_DRI_VERSION_MAJOR 0xff000000
#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
#define BP_DRI_VERSION_MINOR 16
#define BM_DRI_VERSION_MINOR 0xff0000
#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
#define BP_DRI_VERSION_STEP 0
#define BM_DRI_VERSION_STEP 0xffff
#define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff)
#endif /* __HEADERGEN__STMP3700__DRI__H__ */
|