summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/s5l8700/kernel-s5l8700.c
blob: 16a4f972399e0acfd06e0be55421b11024ee9d58 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * $Id$
 *
 * Copyright © 2009 Bertrik Sikken
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#include "config.h"
#include "system.h"
#include "kernel.h"

/*  S5L8700 driver for the kernel timer

    Timer B is configured as a 10 kHz timer (assuming PCLK = 48 MHz)
 */

void INT_TIMERB(void)
{
    /* clear interrupt */
    TBCON = TBCON;

    call_tick_tasks();  /* Run through the list of tick tasks */
}

void tick_start(unsigned int interval_in_ms)
{
    int cycles = 10 * interval_in_ms;
    
    /* enable timer clock */
    PWRCON &= ~(1 << 4);
    
    /* configure timer for 10 kHz */
    TBCMD = (1 << 1);   /* TB_CLR */
    TBPRE = 300 - 1;    /* prescaler for 48 MHz PCLK */
    TBCON = (0 << 13) | /* TB_INT1_EN */
            (1 << 12) | /* TB_INT0_EN */
            (0 << 11) | /* TB_START */
            (2 << 8) |  /* TB_CS = PCLK / 16 */
            (0 << 4);   /* TB_MODE_SEL = interval mode */
    TBDATA0 = cycles;   /* set interval period */
    TBCMD = (1 << 0);   /* TB_EN */

    /* enable timer interrupt */
    INTMSK |= INTMSK_TIMERB;
}