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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_PWR_H__
#define __HEADERGEN_PWR_H__
#include "macro.h"
#define STA_PWR (0x58024800)
#define REG_PWR_CR1 st_reg(PWR_CR1)
#define STA_PWR_CR1 (0x58024800 + 0x0)
#define STO_PWR_CR1 (0x0)
#define STT_PWR_CR1 STIO_32_RW
#define STN_PWR_CR1 PWR_CR1
#define BP_PWR_CR1_ALS 17
#define BM_PWR_CR1_ALS 0x60000
#define BF_PWR_CR1_ALS(v) (((v) & 0x3) << 17)
#define BFM_PWR_CR1_ALS(v) BM_PWR_CR1_ALS
#define BF_PWR_CR1_ALS_V(e) BF_PWR_CR1_ALS(BV_PWR_CR1_ALS__##e)
#define BFM_PWR_CR1_ALS_V(v) BM_PWR_CR1_ALS
#define BP_PWR_CR1_SVOS 14
#define BM_PWR_CR1_SVOS 0xc000
#define BF_PWR_CR1_SVOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_CR1_SVOS(v) BM_PWR_CR1_SVOS
#define BF_PWR_CR1_SVOS_V(e) BF_PWR_CR1_SVOS(BV_PWR_CR1_SVOS__##e)
#define BFM_PWR_CR1_SVOS_V(v) BM_PWR_CR1_SVOS
#define BP_PWR_CR1_PLS 5
#define BM_PWR_CR1_PLS 0xe0
#define BF_PWR_CR1_PLS(v) (((v) & 0x7) << 5)
#define BFM_PWR_CR1_PLS(v) BM_PWR_CR1_PLS
#define BF_PWR_CR1_PLS_V(e) BF_PWR_CR1_PLS(BV_PWR_CR1_PLS__##e)
#define BFM_PWR_CR1_PLS_V(v) BM_PWR_CR1_PLS
#define BP_PWR_CR1_AVDEN 16
#define BM_PWR_CR1_AVDEN 0x10000
#define BF_PWR_CR1_AVDEN(v) (((v) & 0x1) << 16)
#define BFM_PWR_CR1_AVDEN(v) BM_PWR_CR1_AVDEN
#define BF_PWR_CR1_AVDEN_V(e) BF_PWR_CR1_AVDEN(BV_PWR_CR1_AVDEN__##e)
#define BFM_PWR_CR1_AVDEN_V(v) BM_PWR_CR1_AVDEN
#define BP_PWR_CR1_FLPS 9
#define BM_PWR_CR1_FLPS 0x200
#define BF_PWR_CR1_FLPS(v) (((v) & 0x1) << 9)
#define BFM_PWR_CR1_FLPS(v) BM_PWR_CR1_FLPS
#define BF_PWR_CR1_FLPS_V(e) BF_PWR_CR1_FLPS(BV_PWR_CR1_FLPS__##e)
#define BFM_PWR_CR1_FLPS_V(v) BM_PWR_CR1_FLPS
#define BP_PWR_CR1_DBP 8
#define BM_PWR_CR1_DBP 0x100
#define BF_PWR_CR1_DBP(v) (((v) & 0x1) << 8)
#define BFM_PWR_CR1_DBP(v) BM_PWR_CR1_DBP
#define BF_PWR_CR1_DBP_V(e) BF_PWR_CR1_DBP(BV_PWR_CR1_DBP__##e)
#define BFM_PWR_CR1_DBP_V(v) BM_PWR_CR1_DBP
#define BP_PWR_CR1_PVDE 4
#define BM_PWR_CR1_PVDE 0x10
#define BF_PWR_CR1_PVDE(v) (((v) & 0x1) << 4)
#define BFM_PWR_CR1_PVDE(v) BM_PWR_CR1_PVDE
#define BF_PWR_CR1_PVDE_V(e) BF_PWR_CR1_PVDE(BV_PWR_CR1_PVDE__##e)
#define BFM_PWR_CR1_PVDE_V(v) BM_PWR_CR1_PVDE
#define BP_PWR_CR1_LPDS 0
#define BM_PWR_CR1_LPDS 0x1
#define BF_PWR_CR1_LPDS(v) (((v) & 0x1) << 0)
#define BFM_PWR_CR1_LPDS(v) BM_PWR_CR1_LPDS
#define BF_PWR_CR1_LPDS_V(e) BF_PWR_CR1_LPDS(BV_PWR_CR1_LPDS__##e)
#define BFM_PWR_CR1_LPDS_V(v) BM_PWR_CR1_LPDS
#define REG_PWR_CSR1 st_reg(PWR_CSR1)
#define STA_PWR_CSR1 (0x58024800 + 0x4)
#define STO_PWR_CSR1 (0x4)
#define STT_PWR_CSR1 STIO_32_RW
#define STN_PWR_CSR1 PWR_CSR1
#define BP_PWR_CSR1_ACTVOS 14
#define BM_PWR_CSR1_ACTVOS 0xc000
#define BF_PWR_CSR1_ACTVOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_CSR1_ACTVOS(v) BM_PWR_CSR1_ACTVOS
#define BF_PWR_CSR1_ACTVOS_V(e) BF_PWR_CSR1_ACTVOS(BV_PWR_CSR1_ACTVOS__##e)
#define BFM_PWR_CSR1_ACTVOS_V(v) BM_PWR_CSR1_ACTVOS
#define BP_PWR_CSR1_AVDO 16
#define BM_PWR_CSR1_AVDO 0x10000
#define BF_PWR_CSR1_AVDO(v) (((v) & 0x1) << 16)
#define BFM_PWR_CSR1_AVDO(v) BM_PWR_CSR1_AVDO
#define BF_PWR_CSR1_AVDO_V(e) BF_PWR_CSR1_AVDO(BV_PWR_CSR1_AVDO__##e)
#define BFM_PWR_CSR1_AVDO_V(v) BM_PWR_CSR1_AVDO
#define BP_PWR_CSR1_ACTVOSRDY 13
#define BM_PWR_CSR1_ACTVOSRDY 0x2000
#define BF_PWR_CSR1_ACTVOSRDY(v) (((v) & 0x1) << 13)
#define BFM_PWR_CSR1_ACTVOSRDY(v) BM_PWR_CSR1_ACTVOSRDY
#define BF_PWR_CSR1_ACTVOSRDY_V(e) BF_PWR_CSR1_ACTVOSRDY(BV_PWR_CSR1_ACTVOSRDY__##e)
#define BFM_PWR_CSR1_ACTVOSRDY_V(v) BM_PWR_CSR1_ACTVOSRDY
#define BP_PWR_CSR1_PVDO 4
#define BM_PWR_CSR1_PVDO 0x10
#define BF_PWR_CSR1_PVDO(v) (((v) & 0x1) << 4)
#define BFM_PWR_CSR1_PVDO(v) BM_PWR_CSR1_PVDO
#define BF_PWR_CSR1_PVDO_V(e) BF_PWR_CSR1_PVDO(BV_PWR_CSR1_PVDO__##e)
#define BFM_PWR_CSR1_PVDO_V(v) BM_PWR_CSR1_PVDO
#define REG_PWR_CR3 st_reg(PWR_CR3)
#define STA_PWR_CR3 (0x58024800 + 0xc)
#define STO_PWR_CR3 (0xc)
#define STT_PWR_CR3 STIO_32_RW
#define STN_PWR_CR3 PWR_CR3
#define BP_PWR_CR3_USB33RDY 26
#define BM_PWR_CR3_USB33RDY 0x4000000
#define BF_PWR_CR3_USB33RDY(v) (((v) & 0x1) << 26)
#define BFM_PWR_CR3_USB33RDY(v) BM_PWR_CR3_USB33RDY
#define BF_PWR_CR3_USB33RDY_V(e) BF_PWR_CR3_USB33RDY(BV_PWR_CR3_USB33RDY__##e)
#define BFM_PWR_CR3_USB33RDY_V(v) BM_PWR_CR3_USB33RDY
#define BP_PWR_CR3_USBREGEN 25
#define BM_PWR_CR3_USBREGEN 0x2000000
#define BF_PWR_CR3_USBREGEN(v) (((v) & 0x1) << 25)
#define BFM_PWR_CR3_USBREGEN(v) BM_PWR_CR3_USBREGEN
#define BF_PWR_CR3_USBREGEN_V(e) BF_PWR_CR3_USBREGEN(BV_PWR_CR3_USBREGEN__##e)
#define BFM_PWR_CR3_USBREGEN_V(v) BM_PWR_CR3_USBREGEN
#define BP_PWR_CR3_USB33DEN 24
#define BM_PWR_CR3_USB33DEN 0x1000000
#define BF_PWR_CR3_USB33DEN(v) (((v) & 0x1) << 24)
#define BFM_PWR_CR3_USB33DEN(v) BM_PWR_CR3_USB33DEN
#define BF_PWR_CR3_USB33DEN_V(e) BF_PWR_CR3_USB33DEN(BV_PWR_CR3_USB33DEN__##e)
#define BFM_PWR_CR3_USB33DEN_V(v) BM_PWR_CR3_USB33DEN
#define BP_PWR_CR3_VBRS 9
#define BM_PWR_CR3_VBRS 0x200
#define BF_PWR_CR3_VBRS(v) (((v) & 0x1) << 9)
#define BFM_PWR_CR3_VBRS(v) BM_PWR_CR3_VBRS
#define BF_PWR_CR3_VBRS_V(e) BF_PWR_CR3_VBRS(BV_PWR_CR3_VBRS__##e)
#define BFM_PWR_CR3_VBRS_V(v) BM_PWR_CR3_VBRS
#define BP_PWR_CR3_VBE 8
#define BM_PWR_CR3_VBE 0x100
#define BF_PWR_CR3_VBE(v) (((v) & 0x1) << 8)
#define BFM_PWR_CR3_VBE(v) BM_PWR_CR3_VBE
#define BF_PWR_CR3_VBE_V(e) BF_PWR_CR3_VBE(BV_PWR_CR3_VBE__##e)
#define BFM_PWR_CR3_VBE_V(v) BM_PWR_CR3_VBE
#define BP_PWR_CR3_SCUEN 2
#define BM_PWR_CR3_SCUEN 0x4
#define BF_PWR_CR3_SCUEN(v) (((v) & 0x1) << 2)
#define BFM_PWR_CR3_SCUEN(v) BM_PWR_CR3_SCUEN
#define BF_PWR_CR3_SCUEN_V(e) BF_PWR_CR3_SCUEN(BV_PWR_CR3_SCUEN__##e)
#define BFM_PWR_CR3_SCUEN_V(v) BM_PWR_CR3_SCUEN
#define BP_PWR_CR3_LDOEN 1
#define BM_PWR_CR3_LDOEN 0x2
#define BF_PWR_CR3_LDOEN(v) (((v) & 0x1) << 1)
#define BFM_PWR_CR3_LDOEN(v) BM_PWR_CR3_LDOEN
#define BF_PWR_CR3_LDOEN_V(e) BF_PWR_CR3_LDOEN(BV_PWR_CR3_LDOEN__##e)
#define BFM_PWR_CR3_LDOEN_V(v) BM_PWR_CR3_LDOEN
#define BP_PWR_CR3_BYPASS 0
#define BM_PWR_CR3_BYPASS 0x1
#define BF_PWR_CR3_BYPASS(v) (((v) & 0x1) << 0)
#define BFM_PWR_CR3_BYPASS(v) BM_PWR_CR3_BYPASS
#define BF_PWR_CR3_BYPASS_V(e) BF_PWR_CR3_BYPASS(BV_PWR_CR3_BYPASS__##e)
#define BFM_PWR_CR3_BYPASS_V(v) BM_PWR_CR3_BYPASS
#define REG_PWR_D3CR st_reg(PWR_D3CR)
#define STA_PWR_D3CR (0x58024800 + 0x18)
#define STO_PWR_D3CR (0x18)
#define STT_PWR_D3CR STIO_32_RW
#define STN_PWR_D3CR PWR_D3CR
#define BP_PWR_D3CR_VOS 14
#define BM_PWR_D3CR_VOS 0xc000
#define BV_PWR_D3CR_VOS__VOS3 0x1
#define BV_PWR_D3CR_VOS__VOS2 0x2
#define BV_PWR_D3CR_VOS__VOS1 0x3
#define BF_PWR_D3CR_VOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_D3CR_VOS(v) BM_PWR_D3CR_VOS
#define BF_PWR_D3CR_VOS_V(e) BF_PWR_D3CR_VOS(BV_PWR_D3CR_VOS__##e)
#define BFM_PWR_D3CR_VOS_V(v) BM_PWR_D3CR_VOS
#define BP_PWR_D3CR_VOSRDY 13
#define BM_PWR_D3CR_VOSRDY 0x2000
#define BF_PWR_D3CR_VOSRDY(v) (((v) & 0x1) << 13)
#define BFM_PWR_D3CR_VOSRDY(v) BM_PWR_D3CR_VOSRDY
#define BF_PWR_D3CR_VOSRDY_V(e) BF_PWR_D3CR_VOSRDY(BV_PWR_D3CR_VOSRDY__##e)
#define BFM_PWR_D3CR_VOSRDY_V(v) BM_PWR_D3CR_VOSRDY
#endif /* __HEADERGEN_PWR_H__*/
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