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/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * stm32h743 version: 1.0
 * stm32h743 authors: Aidan MacDonald
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_RCC_H__
#define __HEADERGEN_RCC_H__

#include "macro.h"

#define STA_RCC (0x58024400)

#define REG_RCC_CR                  st_reg(RCC_CR)
#define STA_RCC_CR                  (0x58024400 + 0x0)
#define STO_RCC_CR                  (0x0)
#define STT_RCC_CR                  STIO_32_RW
#define STN_RCC_CR                  RCC_CR
#define BP_RCC_CR_HSIDIV            3
#define BM_RCC_CR_HSIDIV            0x18
#define BF_RCC_CR_HSIDIV(v)         (((v) & 0x3) << 3)
#define BFM_RCC_CR_HSIDIV(v)        BM_RCC_CR_HSIDIV
#define BF_RCC_CR_HSIDIV_V(e)       BF_RCC_CR_HSIDIV(BV_RCC_CR_HSIDIV__##e)
#define BFM_RCC_CR_HSIDIV_V(v)      BM_RCC_CR_HSIDIV
#define BP_RCC_CR_PLL3RDY           29
#define BM_RCC_CR_PLL3RDY           0x20000000
#define BF_RCC_CR_PLL3RDY(v)        (((v) & 0x1) << 29)
#define BFM_RCC_CR_PLL3RDY(v)       BM_RCC_CR_PLL3RDY
#define BF_RCC_CR_PLL3RDY_V(e)      BF_RCC_CR_PLL3RDY(BV_RCC_CR_PLL3RDY__##e)
#define BFM_RCC_CR_PLL3RDY_V(v)     BM_RCC_CR_PLL3RDY
#define BP_RCC_CR_PLL3ON            28
#define BM_RCC_CR_PLL3ON            0x10000000
#define BF_RCC_CR_PLL3ON(v)         (((v) & 0x1) << 28)
#define BFM_RCC_CR_PLL3ON(v)        BM_RCC_CR_PLL3ON
#define BF_RCC_CR_PLL3ON_V(e)       BF_RCC_CR_PLL3ON(BV_RCC_CR_PLL3ON__##e)
#define BFM_RCC_CR_PLL3ON_V(v)      BM_RCC_CR_PLL3ON
#define BP_RCC_CR_PLL2RDY           27
#define BM_RCC_CR_PLL2RDY           0x8000000
#define BF_RCC_CR_PLL2RDY(v)        (((v) & 0x1) << 27)
#define BFM_RCC_CR_PLL2RDY(v)       BM_RCC_CR_PLL2RDY
#define BF_RCC_CR_PLL2RDY_V(e)      BF_RCC_CR_PLL2RDY(BV_RCC_CR_PLL2RDY__##e)
#define BFM_RCC_CR_PLL2RDY_V(v)     BM_RCC_CR_PLL2RDY
#define BP_RCC_CR_PLL2ON            26
#define BM_RCC_CR_PLL2ON            0x4000000
#define BF_RCC_CR_PLL2ON(v)         (((v) & 0x1) << 26)
#define BFM_RCC_CR_PLL2ON(v)        BM_RCC_CR_PLL2ON
#define BF_RCC_CR_PLL2ON_V(e)       BF_RCC_CR_PLL2ON(BV_RCC_CR_PLL2ON__##e)
#define BFM_RCC_CR_PLL2ON_V(v)      BM_RCC_CR_PLL2ON
#define BP_RCC_CR_PLL1RDY           25
#define BM_RCC_CR_PLL1RDY           0x2000000
#define BF_RCC_CR_PLL1RDY(v)        (((v) & 0x1) << 25)
#define BFM_RCC_CR_PLL1RDY(v)       BM_RCC_CR_PLL1RDY
#define BF_RCC_CR_PLL1RDY_V(e)      BF_RCC_CR_PLL1RDY(BV_RCC_CR_PLL1RDY__##e)
#define BFM_RCC_CR_PLL1RDY_V(v)     BM_RCC_CR_PLL1RDY
#define BP_RCC_CR_PLL1ON            24
#define BM_RCC_CR_PLL1ON            0x1000000
#define BF_RCC_CR_PLL1ON(v)         (((v) & 0x1) << 24)
#define BFM_RCC_CR_PLL1ON(v)        BM_RCC_CR_PLL1ON
#define BF_RCC_CR_PLL1ON_V(e)       BF_RCC_CR_PLL1ON(BV_RCC_CR_PLL1ON__##e)
#define BFM_RCC_CR_PLL1ON_V(v)      BM_RCC_CR_PLL1ON
#define BP_RCC_CR_HSECSSON          19
#define BM_RCC_CR_HSECSSON          0x80000
#define BF_RCC_CR_HSECSSON(v)       (((v) & 0x1) << 19)
#define BFM_RCC_CR_HSECSSON(v)      BM_RCC_CR_HSECSSON
#define BF_RCC_CR_HSECSSON_V(e)     BF_RCC_CR_HSECSSON(BV_RCC_CR_HSECSSON__##e)
#define BFM_RCC_CR_HSECSSON_V(v)    BM_RCC_CR_HSECSSON
#define BP_RCC_CR_HSEBYP            18
#define BM_RCC_CR_HSEBYP            0x40000
#define BF_RCC_CR_HSEBYP(v)         (((v) & 0x1) << 18)
#define BFM_RCC_CR_HSEBYP(v)        BM_RCC_CR_HSEBYP
#define BF_RCC_CR_HSEBYP_V(e)       BF_RCC_CR_HSEBYP(BV_RCC_CR_HSEBYP__##e)
#define BFM_RCC_CR_HSEBYP_V(v)      BM_RCC_CR_HSEBYP
#define BP_RCC_CR_HSERDY            17
#define BM_RCC_CR_HSERDY            0x20000
#define BF_RCC_CR_HSERDY(v)         (((v) & 0x1) << 17)
#define BFM_RCC_CR_HSERDY(v)        BM_RCC_CR_HSERDY
#define BF_RCC_CR_HSERDY_V(e)       BF_RCC_CR_HSERDY(BV_RCC_CR_HSERDY__##e)
#define BFM_RCC_CR_HSERDY_V(v)      BM_RCC_CR_HSERDY
#define BP_RCC_CR_HSEON             16
#define BM_RCC_CR_HSEON             0x10000
#define BF_RCC_CR_HSEON(v)          (((v) & 0x1) << 16)
#define BFM_RCC_CR_HSEON(v)         BM_RCC_CR_HSEON
#define BF_RCC_CR_HSEON_V(e)        BF_RCC_CR_HSEON(BV_RCC_CR_HSEON__##e)
#define BFM_RCC_CR_HSEON_V(v)       BM_RCC_CR_HSEON
#define BP_RCC_CR_D2CKRDY           15
#define BM_RCC_CR_D2CKRDY           0x8000
#define BF_RCC_CR_D2CKRDY(v)        (((v) & 0x1) << 15)
#define BFM_RCC_CR_D2CKRDY(v)       BM_RCC_CR_D2CKRDY
#define BF_RCC_CR_D2CKRDY_V(e)      BF_RCC_CR_D2CKRDY(BV_RCC_CR_D2CKRDY__##e)
#define BFM_RCC_CR_D2CKRDY_V(v)     BM_RCC_CR_D2CKRDY
#define BP_RCC_CR_D1CKRDY           14
#define BM_RCC_CR_D1CKRDY           0x4000
#define BF_RCC_CR_D1CKRDY(v)        (((v) & 0x1) << 14)
#define BFM_RCC_CR_D1CKRDY(v)       BM_RCC_CR_D1CKRDY
#define BF_RCC_CR_D1CKRDY_V(e)      BF_RCC_CR_D1CKRDY(BV_RCC_CR_D1CKRDY__##e)
#define BFM_RCC_CR_D1CKRDY_V(v)     BM_RCC_CR_D1CKRDY
#define BP_RCC_CR_HSI48RDY          13
#define BM_RCC_CR_HSI48RDY          0x2000
#define BF_RCC_CR_HSI48RDY(v)       (((v) & 0x1) << 13)
#define BFM_RCC_CR_HSI48RDY(v)      BM_RCC_CR_HSI48RDY
#define BF_RCC_CR_HSI48RDY_V(e)     BF_RCC_CR_HSI48RDY(BV_RCC_CR_HSI48RDY__##e)
#define BFM_RCC_CR_HSI48RDY_V(v)    BM_RCC_CR_HSI48RDY
#define BP_RCC_CR_HSI48ON           12
#define BM_RCC_CR_HSI48ON           0x1000
#define BF_RCC_CR_HSI48ON(v)        (((v) & 0x1) << 12)
#define BFM_RCC_CR_HSI48ON(v)       BM_RCC_CR_HSI48ON
#define BF_RCC_CR_HSI48ON_V(e)      BF_RCC_CR_HSI48ON(BV_RCC_CR_HSI48ON__##e)
#define BFM_RCC_CR_HSI48ON_V(v)     BM_RCC_CR_HSI48ON
#define BP_RCC_CR_CSIKERON          9
#define BM_RCC_CR_CSIKERON          0x200
#define BF_RCC_CR_CSIKERON(v)       (((v) & 0x1) << 9)
#define BFM_RCC_CR_CSIKERON(v)      BM_RCC_CR_CSIKERON
#define BF_RCC_CR_CSIKERON_V(e)     BF_RCC_CR_CSIKERON(BV_RCC_CR_CSIKERON__##e)
#define BFM_RCC_CR_CSIKERON_V(v)    BM_RCC_CR_CSIKERON
#define BP_RCC_CR_CSIRDY            8
#define BM_RCC_CR_CSIRDY            0x100
#define BF_RCC_CR_CSIRDY(v)         (((v) & 0x1) << 8)
#define BFM_RCC_CR_CSIRDY(v)        BM_RCC_CR_CSIRDY
#define BF_RCC_CR_CSIRDY_V(e)       BF_RCC_CR_CSIRDY(BV_RCC_CR_CSIRDY__##e)
#define BFM_RCC_CR_CSIRDY_V(v)      BM_RCC_CR_CSIRDY
#define BP_RCC_CR_CSION             7
#define BM_RCC_CR_CSION             0x80
#define BF_RCC_CR_CSION(v)          (((v) & 0x1) << 7)
#define BFM_RCC_CR_CSION(v)         BM_RCC_CR_CSION
#define BF_RCC_CR_CSION_V(e)        BF_RCC_CR_CSION(BV_RCC_CR_CSION__##e)
#define BFM_RCC_CR_CSION_V(v)       BM_RCC_CR_CSION
#define BP_RCC_CR_HSIDIVF           5
#define BM_RCC_CR_HSIDIVF           0x20
#define BF_RCC_CR_HSIDIVF(v)        (((v) & 0x1) << 5)
#define BFM_RCC_CR_HSIDIVF(v)       BM_RCC_CR_HSIDIVF
#define BF_RCC_CR_HSIDIVF_V(e)      BF_RCC_CR_HSIDIVF(BV_RCC_CR_HSIDIVF__##e)
#define BFM_RCC_CR_HSIDIVF_V(v)     BM_RCC_CR_HSIDIVF
#define BP_RCC_CR_HSIRDY            2
#define BM_RCC_CR_HSIRDY            0x4
#define BF_RCC_CR_HSIRDY(v)         (((v) & 0x1) << 2)
#define BFM_RCC_CR_HSIRDY(v)        BM_RCC_CR_HSIRDY
#define BF_RCC_CR_HSIRDY_V(e)       BF_RCC_CR_HSIRDY(BV_RCC_CR_HSIRDY__##e)
#define BFM_RCC_CR_HSIRDY_V(v)      BM_RCC_CR_HSIRDY
#define BP_RCC_CR_HSIKERON          1
#define BM_RCC_CR_HSIKERON          0x2
#define BF_RCC_CR_HSIKERON(v)       (((v) & 0x1) << 1)
#define BFM_RCC_CR_HSIKERON(v)      BM_RCC_CR_HSIKERON
#define BF_RCC_CR_HSIKERON_V(e)     BF_RCC_CR_HSIKERON(BV_RCC_CR_HSIKERON__##e)
#define BFM_RCC_CR_HSIKERON_V(v)    BM_RCC_CR_HSIKERON
#define BP_RCC_CR_HSION             0
#define BM_RCC_CR_HSION             0x1
#define BF_RCC_CR_HSION(v)          (((v) & 0x1) << 0)
#define BFM_RCC_CR_HSION(v)         BM_RCC_CR_HSION
#define BF_RCC_CR_HSION_V(e)        BF_RCC_CR_HSION(BV_RCC_CR_HSION__##e)
#define BFM_RCC_CR_HSION_V(v)       BM_RCC_CR_HSION

#define REG_RCC_CFGR                    st_reg(RCC_CFGR)
#define STA_RCC_CFGR                    (0x58024400 + 0x10)
#define STO_RCC_CFGR                    (0x10)
#define STT_RCC_CFGR                    STIO_32_RW
#define STN_RCC_CFGR                    RCC_CFGR
#define BP_RCC_CFGR_MCO2                29
#define BM_RCC_CFGR_MCO2                0xe0000000
#define BV_RCC_CFGR_MCO2__SYSCLK        0x0
#define BV_RCC_CFGR_MCO2__PLL2P         0x1
#define BV_RCC_CFGR_MCO2__HSE           0x2
#define BV_RCC_CFGR_MCO2__PLL1P         0x3
#define BV_RCC_CFGR_MCO2__CSI           0x4
#define BV_RCC_CFGR_MCO2__LSI           0x5
#define BF_RCC_CFGR_MCO2(v)             (((v) & 0x7) << 29)
#define BFM_RCC_CFGR_MCO2(v)            BM_RCC_CFGR_MCO2
#define BF_RCC_CFGR_MCO2_V(e)           BF_RCC_CFGR_MCO2(BV_RCC_CFGR_MCO2__##e)
#define BFM_RCC_CFGR_MCO2_V(v)          BM_RCC_CFGR_MCO2
#define BP_RCC_CFGR_MCO2PRE             25
#define BM_RCC_CFGR_MCO2PRE             0x1e000000
#define BF_RCC_CFGR_MCO2PRE(v)          (((v) & 0xf) << 25)
#define BFM_RCC_CFGR_MCO2PRE(v)         BM_RCC_CFGR_MCO2PRE
#define BF_RCC_CFGR_MCO2PRE_V(e)        BF_RCC_CFGR_MCO2PRE(BV_RCC_CFGR_MCO2PRE__##e)
#define BFM_RCC_CFGR_MCO2PRE_V(v)       BM_RCC_CFGR_MCO2PRE
#define BP_RCC_CFGR_MCO1                22
#define BM_RCC_CFGR_MCO1                0x1c00000
#define BV_RCC_CFGR_MCO1__HSI           0x0
#define BV_RCC_CFGR_MCO1__LSE           0x1
#define BV_RCC_CFGR_MCO1__HSE           0x2
#define BV_RCC_CFGR_MCO1__PLL1Q         0x3
#define BV_RCC_CFGR_MCO1__HSI48         0x4
#define BF_RCC_CFGR_MCO1(v)             (((v) & 0x7) << 22)
#define BFM_RCC_CFGR_MCO1(v)            BM_RCC_CFGR_MCO1
#define BF_RCC_CFGR_MCO1_V(e)           BF_RCC_CFGR_MCO1(BV_RCC_CFGR_MCO1__##e)
#define BFM_RCC_CFGR_MCO1_V(v)          BM_RCC_CFGR_MCO1
#define BP_RCC_CFGR_MCO1PRE             18
#define BM_RCC_CFGR_MCO1PRE             0x3c0000
#define BF_RCC_CFGR_MCO1PRE(v)          (((v) & 0xf) << 18)
#define BFM_RCC_CFGR_MCO1PRE(v)         BM_RCC_CFGR_MCO1PRE
#define BF_RCC_CFGR_MCO1PRE_V(e)        BF_RCC_CFGR_MCO1PRE(BV_RCC_CFGR_MCO1PRE__##e)
#define BFM_RCC_CFGR_MCO1PRE_V(v)       BM_RCC_CFGR_MCO1PRE
#define BP_RCC_CFGR_RTCPRE              8
#define BM_RCC_CFGR_RTCPRE              0x3f00
#define BF_RCC_CFGR_RTCPRE(v)           (((v) & 0x3f) << 8)
#define BFM_RCC_CFGR_RTCPRE(v)          BM_RCC_CFGR_RTCPRE
#define BF_RCC_CFGR_RTCPRE_V(e)         BF_RCC_CFGR_RTCPRE(BV_RCC_CFGR_RTCPRE__##e)
#define BFM_RCC_CFGR_RTCPRE_V(v)        BM_RCC_CFGR_RTCPRE
#define BP_RCC_CFGR_SWS                 3
#define BM_RCC_CFGR_SWS                 0x38
#define BF_RCC_CFGR_SWS(v)              (((v) & 0x7) << 3)
#define BFM_RCC_CFGR_SWS(v)             BM_RCC_CFGR_SWS
#define BF_RCC_CFGR_SWS_V(e)            BF_RCC_CFGR_SWS(BV_RCC_CFGR_SWS__##e)
#define BFM_RCC_CFGR_SWS_V(v)           BM_RCC_CFGR_SWS
#define BP_RCC_CFGR_SW                  0
#define BM_RCC_CFGR_SW                  0x7
#define BV_RCC_CFGR_SW__HSI             0x0
#define BV_RCC_CFGR_SW__CSI             0x1
#define BV_RCC_CFGR_SW__HSE             0x2
#define BV_RCC_CFGR_SW__PLL1P           0x3
#define BF_RCC_CFGR_SW(v)               (((v) & 0x7) << 0)
#define BFM_RCC_CFGR_SW(v)              BM_RCC_CFGR_SW
#define BF_RCC_CFGR_SW_V(e)             BF_RCC_CFGR_SW(BV_RCC_CFGR_SW__##e)
#define BFM_RCC_CFGR_SW_V(v)            BM_RCC_CFGR_SW
#define BP_RCC_CFGR_TIMPRE              15
#define BM_RCC_CFGR_TIMPRE              0x8000
#define BF_RCC_CFGR_TIMPRE(v)           (((v) & 0x1) << 15)
#define BFM_RCC_CFGR_TIMPRE(v)          BM_RCC_CFGR_TIMPRE
#define BF_RCC_CFGR_TIMPRE_V(e)         BF_RCC_CFGR_TIMPRE(BV_RCC_CFGR_TIMPRE__##e)
#define BFM_RCC_CFGR_TIMPRE_V(v)        BM_RCC_CFGR_TIMPRE
#define BP_RCC_CFGR_HRTIMSEL            14
#define BM_RCC_CFGR_HRTIMSEL            0x4000
#define BF_RCC_CFGR_HRTIMSEL(v)         (((v) & 0x1) << 14)
#define BFM_RCC_CFGR_HRTIMSEL(v)        BM_RCC_CFGR_HRTIMSEL
#define BF_RCC_CFGR_HRTIMSEL_V(e)       BF_RCC_CFGR_HRTIMSEL(BV_RCC_CFGR_HRTIMSEL__##e)
#define BFM_RCC_CFGR_HRTIMSEL_V(v)      BM_RCC_CFGR_HRTIMSEL
#define BP_RCC_CFGR_STOPKERWUCK         7
#define BM_RCC_CFGR_STOPKERWUCK         0x80
#define BF_RCC_CFGR_STOPKERWUCK(v)      (((v) & 0x1) << 7)
#define BFM_RCC_CFGR_STOPKERWUCK(v)     BM_RCC_CFGR_STOPKERWUCK
#define BF_RCC_CFGR_STOPKERWUCK_V(e)    BF_RCC_CFGR_STOPKERWUCK(BV_RCC_CFGR_STOPKERWUCK__##e)
#define BFM_RCC_CFGR_STOPKERWUCK_V(v)   BM_RCC_CFGR_STOPKERWUCK
#define BP_RCC_CFGR_STOPWUCK            6
#define BM_RCC_CFGR_STOPWUCK            0x40
#define BF_RCC_CFGR_STOPWUCK(v)         (((v) & 0x1) << 6)
#define BFM_RCC_CFGR_STOPWUCK(v)        BM_RCC_CFGR_STOPWUCK
#define BF_RCC_CFGR_STOPWUCK_V(e)       BF_RCC_CFGR_STOPWUCK(BV_RCC_CFGR_STOPWUCK__##e)
#define BFM_RCC_CFGR_STOPWUCK_V(v)      BM_RCC_CFGR_STOPWUCK

#define REG_RCC_D1CFGR              st_reg(RCC_D1CFGR)
#define STA_RCC_D1CFGR              (0x58024400 + 0x18)
#define STO_RCC_D1CFGR              (0x18)
#define STT_RCC_D1CFGR              STIO_32_RW
#define STN_RCC_D1CFGR              RCC_D1CFGR
#define BP_RCC_D1CFGR_D1CPRE        8
#define BM_RCC_D1CFGR_D1CPRE        0xf00
#define BF_RCC_D1CFGR_D1CPRE(v)     (((v) & 0xf) << 8)
#define BFM_RCC_D1CFGR_D1CPRE(v)    BM_RCC_D1CFGR_D1CPRE
#define BF_RCC_D1CFGR_D1CPRE_V(e)   BF_RCC_D1CFGR_D1CPRE(BV_RCC_D1CFGR_D1CPRE__##e)
#define BFM_RCC_D1CFGR_D1CPRE_V(v)  BM_RCC_D1CFGR_D1CPRE
#define BP_RCC_D1CFGR_D1PPRE        4
#define BM_RCC_D1CFGR_D1PPRE        0x70
#define BF_RCC_D1CFGR_D1PPRE(v)     (((v) & 0x7) << 4)
#define BFM_RCC_D1CFGR_D1PPRE(v)    BM_RCC_D1CFGR_D1PPRE
#define BF_RCC_D1CFGR_D1PPRE_V(e)   BF_RCC_D1CFGR_D1PPRE(BV_RCC_D1CFGR_D1PPRE__##e)
#define BFM_RCC_D1CFGR_D1PPRE_V(v)  BM_RCC_D1CFGR_D1PPRE
#define BP_RCC_D1CFGR_HPRE          0
#define BM_RCC_D1CFGR_HPRE          0x1f
#define BF_RCC_D1CFGR_HPRE(v)       (((v) & 0x1f) << 0)
#define BFM_RCC_D1CFGR_HPRE(v)      BM_RCC_D1CFGR_HPRE
#define BF_RCC_D1CFGR_HPRE_V(e)     BF_RCC_D1CFGR_HPRE(BV_RCC_D1CFGR_HPRE__##e)
#define BFM_RCC_D1CFGR_HPRE_V(v)    BM_RCC_D1CFGR_HPRE

#define REG_RCC_D2CFGR              st_reg(RCC_D2CFGR)
#define STA_RCC_D2CFGR              (0x58024400 + 0x1c)
#define STO_RCC_D2CFGR              (0x1c)
#define STT_RCC_D2CFGR              STIO_32_RW
#define STN_RCC_D2CFGR              RCC_D2CFGR
#define BP_RCC_D2CFGR_D2PPRE2       8
#define BM_RCC_D2CFGR_D2PPRE2       0x700
#define BF_RCC_D2CFGR_D2PPRE2(v)    (((v) & 0x7) << 8)
#define BFM_RCC_D2CFGR_D2PPRE2(v)   BM_RCC_D2CFGR_D2PPRE2
#define BF_RCC_D2CFGR_D2PPRE2_V(e)  BF_RCC_D2CFGR_D2PPRE2(BV_RCC_D2CFGR_D2PPRE2__##e)
#define BFM_RCC_D2CFGR_D2PPRE2_V(v) BM_RCC_D2CFGR_D2PPRE2
#define BP_RCC_D2CFGR_D2PPRE1       4
#define BM_RCC_D2CFGR_D2PPRE1       0x70
#define BF_RCC_D2CFGR_D2PPRE1(v)    (((v) & 0x7) << 4)
#define BFM_RCC_D2CFGR_D2PPRE1(v)   BM_RCC_D2CFGR_D2PPRE1
#define BF_RCC_D2CFGR_D2PPRE1_V(e)  BF_RCC_D2CFGR_D2PPRE1(BV_RCC_D2CFGR_D2PPRE1__##e)
#define BFM_RCC_D2CFGR_D2PPRE1_V(v) BM_RCC_D2CFGR_D2PPRE1

#define REG_RCC_D3CFGR              st_reg(RCC_D3CFGR)
#define STA_RCC_D3CFGR              (0x58024400 + 0x20)
#define STO_RCC_D3CFGR              (0x20)
#define STT_RCC_D3CFGR              STIO_32_RW
#define STN_RCC_D3CFGR              RCC_D3CFGR
#define BP_RCC_D3CFGR_D3PPRE        4
#define BM_RCC_D3CFGR_D3PPRE        0x70
#define BF_RCC_D3CFGR_D3PPRE(v)     (((v) & 0x7) << 4)
#define BFM_RCC_D3CFGR_D3PPRE(v)    BM_RCC_D3CFGR_D3PPRE
#define BF_RCC_D3CFGR_D3PPRE_V(e)   BF_RCC_D3CFGR_D3PPRE(BV_RCC_D3CFGR_D3PPRE__##e)
#define BFM_RCC_D3CFGR_D3PPRE_V(v)  BM_RCC_D3CFGR_D3PPRE

#define REG_RCC_PLLCKSELR               st_reg(RCC_PLLCKSELR)
#define STA_RCC_PLLCKSELR               (0x58024400 + 0x28)
#define STO_RCC_PLLCKSELR               (0x28)
#define STT_RCC_PLLCKSELR               STIO_32_RW
#define STN_RCC_PLLCKSELR               RCC_PLLCKSELR
#define BP_RCC_PLLCKSELR_DIVM3          20
#define BM_RCC_PLLCKSELR_DIVM3          0x3f00000
#define BF_RCC_PLLCKSELR_DIVM3(v)       (((v) & 0x3f) << 20)
#define BFM_RCC_PLLCKSELR_DIVM3(v)      BM_RCC_PLLCKSELR_DIVM3
#define BF_RCC_PLLCKSELR_DIVM3_V(e)     BF_RCC_PLLCKSELR_DIVM3(BV_RCC_PLLCKSELR_DIVM3__##e)
#define BFM_RCC_PLLCKSELR_DIVM3_V(v)    BM_RCC_PLLCKSELR_DIVM3
#define BP_RCC_PLLCKSELR_DIVM2          12
#define BM_RCC_PLLCKSELR_DIVM2          0x3f000
#define BF_RCC_PLLCKSELR_DIVM2(v)       (((v) & 0x3f) << 12)
#define BFM_RCC_PLLCKSELR_DIVM2(v)      BM_RCC_PLLCKSELR_DIVM2
#define BF_RCC_PLLCKSELR_DIVM2_V(e)     BF_RCC_PLLCKSELR_DIVM2(BV_RCC_PLLCKSELR_DIVM2__##e)
#define BFM_RCC_PLLCKSELR_DIVM2_V(v)    BM_RCC_PLLCKSELR_DIVM2
#define BP_RCC_PLLCKSELR_DIVM1          4
#define BM_RCC_PLLCKSELR_DIVM1          0x3f0
#define BF_RCC_PLLCKSELR_DIVM1(v)       (((v) & 0x3f) << 4)
#define BFM_RCC_PLLCKSELR_DIVM1(v)      BM_RCC_PLLCKSELR_DIVM1
#define BF_RCC_PLLCKSELR_DIVM1_V(e)     BF_RCC_PLLCKSELR_DIVM1(BV_RCC_PLLCKSELR_DIVM1__##e)
#define BFM_RCC_PLLCKSELR_DIVM1_V(v)    BM_RCC_PLLCKSELR_DIVM1
#define BP_RCC_PLLCKSELR_PLLSRC         0
#define BM_RCC_PLLCKSELR_PLLSRC         0x3
#define BV_RCC_PLLCKSELR_PLLSRC__HSI    0x0
#define BV_RCC_PLLCKSELR_PLLSRC__CSI    0x1
#define BV_RCC_PLLCKSELR_PLLSRC__HSE    0x2
#define BV_RCC_PLLCKSELR_PLLSRC__NONE   0x3
#define BF_RCC_PLLCKSELR_PLLSRC(v)      (((v) & 0x3) << 0)
#define BFM_RCC_PLLCKSELR_PLLSRC(v)     BM_RCC_PLLCKSELR_PLLSRC
#define BF_RCC_PLLCKSELR_PLLSRC_V(e)    BF_RCC_PLLCKSELR_PLLSRC(BV_RCC_PLLCKSELR_PLLSRC__##e)
#define BFM_RCC_PLLCKSELR_PLLSRC_V(v)   BM_RCC_PLLCKSELR_PLLSRC

#define REG_RCC_PLLCFGR                     st_reg(RCC_PLLCFGR)
#define STA_RCC_PLLCFGR                     (0x58024400 + 0x2c)
#define STO_RCC_PLLCFGR                     (0x2c)
#define STT_RCC_PLLCFGR                     STIO_32_RW
#define STN_RCC_PLLCFGR                     RCC_PLLCFGR
#define BP_RCC_PLLCFGR_PLL3RGE              10
#define BM_RCC_PLLCFGR_PLL3RGE              0xc00
#define BV_RCC_PLLCFGR_PLL3RGE__1_2MHZ      0x0
#define BV_RCC_PLLCFGR_PLL3RGE__2_4MHz      0x1
#define BV_RCC_PLLCFGR_PLL3RGE__4_8MHz      0x2
#define BV_RCC_PLLCFGR_PLL3RGE__8_16MHz     0x3
#define BF_RCC_PLLCFGR_PLL3RGE(v)           (((v) & 0x3) << 10)
#define BFM_RCC_PLLCFGR_PLL3RGE(v)          BM_RCC_PLLCFGR_PLL3RGE
#define BF_RCC_PLLCFGR_PLL3RGE_V(e)         BF_RCC_PLLCFGR_PLL3RGE(BV_RCC_PLLCFGR_PLL3RGE__##e)
#define BFM_RCC_PLLCFGR_PLL3RGE_V(v)        BM_RCC_PLLCFGR_PLL3RGE
#define BP_RCC_PLLCFGR_PLL2RGE              6
#define BM_RCC_PLLCFGR_PLL2RGE              0xc0
#define BV_RCC_PLLCFGR_PLL2RGE__1_2MHZ      0x0
#define BV_RCC_PLLCFGR_PLL2RGE__2_4MHz      0x1
#define BV_RCC_PLLCFGR_PLL2RGE__4_8MHz      0x2
#define BV_RCC_PLLCFGR_PLL2RGE__8_16MHz     0x3
#define BF_RCC_PLLCFGR_PLL2RGE(v)           (((v) & 0x3) << 6)
#define BFM_RCC_PLLCFGR_PLL2RGE(v)          BM_RCC_PLLCFGR_PLL2RGE
#define BF_RCC_PLLCFGR_PLL2RGE_V(e)         BF_RCC_PLLCFGR_PLL2RGE(BV_RCC_PLLCFGR_PLL2RGE__##e)
#define BFM_RCC_PLLCFGR_PLL2RGE_V(v)        BM_RCC_PLLCFGR_PLL2RGE
#define BP_RCC_PLLCFGR_PLL1RGE              2
#define BM_RCC_PLLCFGR_PLL1RGE              0xc
#define BV_RCC_PLLCFGR_PLL1RGE__1_2MHZ      0x0
#define BV_RCC_PLLCFGR_PLL1RGE__2_4MHz      0x1
#define BV_RCC_PLLCFGR_PLL1RGE__4_8MHz      0x2
#define BV_RCC_PLLCFGR_PLL1RGE__8_16MHz     0x3
#define BF_RCC_PLLCFGR_PLL1RGE(v)           (((v) & 0x3) << 2)
#define BFM_RCC_PLLCFGR_PLL1RGE(v)          BM_RCC_PLLCFGR_PLL1RGE
#define BF_RCC_PLLCFGR_PLL1RGE_V(e)         BF_RCC_PLLCFGR_PLL1RGE(BV_RCC_PLLCFGR_PLL1RGE__##e)
#define BFM_RCC_PLLCFGR_PLL1RGE_V(v)        BM_RCC_PLLCFGR_PLL1RGE
#define BP_RCC_PLLCFGR_DIVR3EN              24
#define BM_RCC_PLLCFGR_DIVR3EN              0x1000000
#define BF_RCC_PLLCFGR_DIVR3EN(v)           (((v) & 0x1) << 24)
#define BFM_RCC_PLLCFGR_DIVR3EN(v)          BM_RCC_PLLCFGR_DIVR3EN
#define BF_RCC_PLLCFGR_DIVR3EN_V(e)         BF_RCC_PLLCFGR_DIVR3EN(BV_RCC_PLLCFGR_DIVR3EN__##e)
#define BFM_RCC_PLLCFGR_DIVR3EN_V(v)        BM_RCC_PLLCFGR_DIVR3EN
#define BP_RCC_PLLCFGR_DIVQ3EN              23
#define BM_RCC_PLLCFGR_DIVQ3EN              0x800000
#define BF_RCC_PLLCFGR_DIVQ3EN(v)           (((v) & 0x1) << 23)
#define BFM_RCC_PLLCFGR_DIVQ3EN(v)          BM_RCC_PLLCFGR_DIVQ3EN
#define BF_RCC_PLLCFGR_DIVQ3EN_V(e)         BF_RCC_PLLCFGR_DIVQ3EN(BV_RCC_PLLCFGR_DIVQ3EN__##e)
#define BFM_RCC_PLLCFGR_DIVQ3EN_V(v)        BM_RCC_PLLCFGR_DIVQ3EN
#define BP_RCC_PLLCFGR_DIVP3EN              22
#define BM_RCC_PLLCFGR_DIVP3EN              0x400000
#define BF_RCC_PLLCFGR_DIVP3EN(v)           (((v) & 0x1) << 22)
#define BFM_RCC_PLLCFGR_DIVP3EN(v)          BM_RCC_PLLCFGR_DIVP3EN
#define BF_RCC_PLLCFGR_DIVP3EN_V(e)         BF_RCC_PLLCFGR_DIVP3EN(BV_RCC_PLLCFGR_DIVP3EN__##e)
#define BFM_RCC_PLLCFGR_DIVP3EN_V(v)        BM_RCC_PLLCFGR_DIVP3EN
#define BP_RCC_PLLCFGR_DIVR2EN              21
#define BM_RCC_PLLCFGR_DIVR2EN              0x200000
#define BF_RCC_PLLCFGR_DIVR2EN(v)           (((v) & 0x1) << 21)
#define BFM_RCC_PLLCFGR_DIVR2EN(v)          BM_RCC_PLLCFGR_DIVR2EN
#define BF_RCC_PLLCFGR_DIVR2EN_V(e)         BF_RCC_PLLCFGR_DIVR2EN(BV_RCC_PLLCFGR_DIVR2EN__##e)
#define BFM_RCC_PLLCFGR_DIVR2EN_V(v)        BM_RCC_PLLCFGR_DIVR2EN
#define BP_RCC_PLLCFGR_DIVQ2EN              20
#define BM_RCC_PLLCFGR_DIVQ2EN              0x100000
#define BF_RCC_PLLCFGR_DIVQ2EN(v)           (((v) & 0x1) << 20)
#define BFM_RCC_PLLCFGR_DIVQ2EN(v)          BM_RCC_PLLCFGR_DIVQ2EN
#define BF_RCC_PLLCFGR_DIVQ2EN_V(e)         BF_RCC_PLLCFGR_DIVQ2EN(BV_RCC_PLLCFGR_DIVQ2EN__##e)
#define BFM_RCC_PLLCFGR_DIVQ2EN_V(v)        BM_RCC_PLLCFGR_DIVQ2EN
#define BP_RCC_PLLCFGR_DIVP2EN              19
#define BM_RCC_PLLCFGR_DIVP2EN              0x80000
#define BF_RCC_PLLCFGR_DIVP2EN(v)           (((v) & 0x1) << 19)
#define BFM_RCC_PLLCFGR_DIVP2EN(v)          BM_RCC_PLLCFGR_DIVP2EN
#define BF_RCC_PLLCFGR_DIVP2EN_V(e)         BF_RCC_PLLCFGR_DIVP2EN(BV_RCC_PLLCFGR_DIVP2EN__##e)
#define BFM_RCC_PLLCFGR_DIVP2EN_V(v)        BM_RCC_PLLCFGR_DIVP2EN
#define BP_RCC_PLLCFGR_DIVR1EN              18
#define BM_RCC_PLLCFGR_DIVR1EN              0x40000
#define BF_RCC_PLLCFGR_DIVR1EN(v)           (((v) & 0x1) << 18)
#define BFM_RCC_PLLCFGR_DIVR1EN(v)          BM_RCC_PLLCFGR_DIVR1EN
#define BF_RCC_PLLCFGR_DIVR1EN_V(e)         BF_RCC_PLLCFGR_DIVR1EN(BV_RCC_PLLCFGR_DIVR1EN__##e)
#define BFM_RCC_PLLCFGR_DIVR1EN_V(v)        BM_RCC_PLLCFGR_DIVR1EN
#define BP_RCC_PLLCFGR_DIVQ1EN              17
#define BM_RCC_PLLCFGR_DIVQ1EN              0x20000
#define BF_RCC_PLLCFGR_DIVQ1EN(v)           (((v) & 0x1) << 17)
#define BFM_RCC_PLLCFGR_DIVQ1EN(v)          BM_RCC_PLLCFGR_DIVQ1EN
#define BF_RCC_PLLCFGR_DIVQ1EN_V(e)         BF_RCC_PLLCFGR_DIVQ1EN(BV_RCC_PLLCFGR_DIVQ1EN__##e)
#define BFM_RCC_PLLCFGR_DIVQ1EN_V(v)        BM_RCC_PLLCFGR_DIVQ1EN
#define BP_RCC_PLLCFGR_DIVP1EN              16
#define BM_RCC_PLLCFGR_DIVP1EN              0x10000
#define BF_RCC_PLLCFGR_DIVP1EN(v)           (((v) & 0x1) << 16)
#define BFM_RCC_PLLCFGR_DIVP1EN(v)          BM_RCC_PLLCFGR_DIVP1EN
#define BF_RCC_PLLCFGR_DIVP1EN_V(e)         BF_RCC_PLLCFGR_DIVP1EN(BV_RCC_PLLCFGR_DIVP1EN__##e)
#define BFM_RCC_PLLCFGR_DIVP1EN_V(v)        BM_RCC_PLLCFGR_DIVP1EN
#define BP_RCC_PLLCFGR_PLL3VCOSEL           9
#define BM_RCC_PLLCFGR_PLL3VCOSEL           0x200
#define BV_RCC_PLLCFGR_PLL3VCOSEL__WIDE     0x0
#define BV_RCC_PLLCFGR_PLL3VCOSEL__MEDIUM   0x1
#define BF_RCC_PLLCFGR_PLL3VCOSEL(v)        (((v) & 0x1) << 9)
#define BFM_RCC_PLLCFGR_PLL3VCOSEL(v)       BM_RCC_PLLCFGR_PLL3VCOSEL
#define BF_RCC_PLLCFGR_PLL3VCOSEL_V(e)      BF_RCC_PLLCFGR_PLL3VCOSEL(BV_RCC_PLLCFGR_PLL3VCOSEL__##e)
#define BFM_RCC_PLLCFGR_PLL3VCOSEL_V(v)     BM_RCC_PLLCFGR_PLL3VCOSEL
#define BP_RCC_PLLCFGR_PLL3FRACEN           8
#define BM_RCC_PLLCFGR_PLL3FRACEN           0x100
#define BF_RCC_PLLCFGR_PLL3FRACEN(v)        (((v) & 0x1) << 8)
#define BFM_RCC_PLLCFGR_PLL3FRACEN(v)       BM_RCC_PLLCFGR_PLL3FRACEN
#define BF_RCC_PLLCFGR_PLL3FRACEN_V(e)      BF_RCC_PLLCFGR_PLL3FRACEN(BV_RCC_PLLCFGR_PLL3FRACEN__##e)
#define BFM_RCC_PLLCFGR_PLL3FRACEN_V(v)     BM_RCC_PLLCFGR_PLL3FRACEN
#define BP_RCC_PLLCFGR_PLL2VCOSEL           5
#define BM_RCC_PLLCFGR_PLL2VCOSEL           0x20
#define BV_RCC_PLLCFGR_PLL2VCOSEL__WIDE     0x0
#define BV_RCC_PLLCFGR_PLL2VCOSEL__MEDIUM   0x1
#define BF_RCC_PLLCFGR_PLL2VCOSEL(v)        (((v) & 0x1) << 5)
#define BFM_RCC_PLLCFGR_PLL2VCOSEL(v)       BM_RCC_PLLCFGR_PLL2VCOSEL
#define BF_RCC_PLLCFGR_PLL2VCOSEL_V(e)      BF_RCC_PLLCFGR_PLL2VCOSEL(BV_RCC_PLLCFGR_PLL2VCOSEL__##e)
#define BFM_RCC_PLLCFGR_PLL2VCOSEL_V(v)     BM_RCC_PLLCFGR_PLL2VCOSEL
#define BP_RCC_PLLCFGR_PLL2FRACEN           4
#define BM_RCC_PLLCFGR_PLL2FRACEN           0x10
#define BF_RCC_PLLCFGR_PLL2FRACEN(v)        (((v) & 0x1) << 4)
#define BFM_RCC_PLLCFGR_PLL2FRACEN(v)       BM_RCC_PLLCFGR_PLL2FRACEN
#define BF_RCC_PLLCFGR_PLL2FRACEN_V(e)      BF_RCC_PLLCFGR_PLL2FRACEN(BV_RCC_PLLCFGR_PLL2FRACEN__##e)
#define BFM_RCC_PLLCFGR_PLL2FRACEN_V(v)     BM_RCC_PLLCFGR_PLL2FRACEN
#define BP_RCC_PLLCFGR_PLL1VCOSEL           1
#define BM_RCC_PLLCFGR_PLL1VCOSEL           0x2
#define BV_RCC_PLLCFGR_PLL1VCOSEL__WIDE     0x0
#define BV_RCC_PLLCFGR_PLL1VCOSEL__MEDIUM   0x1
#define BF_RCC_PLLCFGR_PLL1VCOSEL(v)        (((v) & 0x1) << 1)
#define BFM_RCC_PLLCFGR_PLL1VCOSEL(v)       BM_RCC_PLLCFGR_PLL1VCOSEL
#define BF_RCC_PLLCFGR_PLL1VCOSEL_V(e)      BF_RCC_PLLCFGR_PLL1VCOSEL(BV_RCC_PLLCFGR_PLL1VCOSEL__##e)
#define BFM_RCC_PLLCFGR_PLL1VCOSEL_V(v)     BM_RCC_PLLCFGR_PLL1VCOSEL
#define BP_RCC_PLLCFGR_PLL1FRACEN           0
#define BM_RCC_PLLCFGR_PLL1FRACEN           0x1
#define BF_RCC_PLLCFGR_PLL1FRACEN(v)        (((v) & 0x1) << 0)
#define BFM_RCC_PLLCFGR_PLL1FRACEN(v)       BM_RCC_PLLCFGR_PLL1FRACEN
#define BF_RCC_PLLCFGR_PLL1FRACEN_V(e)      BF_RCC_PLLCFGR_PLL1FRACEN(BV_RCC_PLLCFGR_PLL1FRACEN__##e)
#define BFM_RCC_PLLCFGR_PLL1FRACEN_V(v)     BM_RCC_PLLCFGR_PLL1FRACEN

#define REG_RCC_PLL1DIVR            st_reg(RCC_PLL1DIVR)
#define STA_RCC_PLL1DIVR            (0x58024400 + 0x30)
#define STO_RCC_PLL1DIVR            (0x30)
#define STT_RCC_PLL1DIVR            STIO_32_RW
#define STN_RCC_PLL1DIVR            RCC_PLL1DIVR
#define BP_RCC_PLL1DIVR_DIVR        24
#define BM_RCC_PLL1DIVR_DIVR        0x7f000000
#define BF_RCC_PLL1DIVR_DIVR(v)     (((v) & 0x7f) << 24)
#define BFM_RCC_PLL1DIVR_DIVR(v)    BM_RCC_PLL1DIVR_DIVR
#define BF_RCC_PLL1DIVR_DIVR_V(e)   BF_RCC_PLL1DIVR_DIVR(BV_RCC_PLL1DIVR_DIVR__##e)
#define BFM_RCC_PLL1DIVR_DIVR_V(v)  BM_RCC_PLL1DIVR_DIVR
#define BP_RCC_PLL1DIVR_DIVQ        16
#define BM_RCC_PLL1DIVR_DIVQ        0x7f0000
#define BF_RCC_PLL1DIVR_DIVQ(v)     (((v) & 0x7f) << 16)
#define BFM_RCC_PLL1DIVR_DIVQ(v)    BM_RCC_PLL1DIVR_DIVQ
#define BF_RCC_PLL1DIVR_DIVQ_V(e)   BF_RCC_PLL1DIVR_DIVQ(BV_RCC_PLL1DIVR_DIVQ__##e)
#define BFM_RCC_PLL1DIVR_DIVQ_V(v)  BM_RCC_PLL1DIVR_DIVQ
#define BP_RCC_PLL1DIVR_DIVP        9
#define BM_RCC_PLL1DIVR_DIVP        0xfe00
#define BF_RCC_PLL1DIVR_DIVP(v)     (((v) & 0x7f) << 9)
#define BFM_RCC_PLL1DIVR_DIVP(v)    BM_RCC_PLL1DIVR_DIVP
#define BF_RCC_PLL1DIVR_DIVP_V(e)   BF_RCC_PLL1DIVR_DIVP(BV_RCC_PLL1DIVR_DIVP__##e)
#define BFM_RCC_PLL1DIVR_DIVP_V(v)  BM_RCC_PLL1DIVR_DIVP
#define BP_RCC_PLL1DIVR_DIVN        0
#define BM_RCC_PLL1DIVR_DIVN        0x1ff
#define BF_RCC_PLL1DIVR_DIVN(v)     (((v) & 0x1ff) << 0)
#define BFM_RCC_PLL1DIVR_DIVN(v)    BM_RCC_PLL1DIVR_DIVN
#define BF_RCC_PLL1DIVR_DIVN_V(e)   BF_RCC_PLL1DIVR_DIVN(BV_RCC_PLL1DIVR_DIVN__##e)
#define BFM_RCC_PLL1DIVR_DIVN_V(v)  BM_RCC_PLL1DIVR_DIVN

#define REG_RCC_PLL2DIVR            st_reg(RCC_PLL2DIVR)
#define STA_RCC_PLL2DIVR            (0x58024400 + 0x38)
#define STO_RCC_PLL2DIVR            (0x38)
#define STT_RCC_PLL2DIVR            STIO_32_RW
#define STN_RCC_PLL2DIVR            RCC_PLL2DIVR
#define BP_RCC_PLL2DIVR_DIVR        24
#define BM_RCC_PLL2DIVR_DIVR        0x7f000000
#define BF_RCC_PLL2DIVR_DIVR(v)     (((v) & 0x7f) << 24)
#define BFM_RCC_PLL2DIVR_DIVR(v)    BM_RCC_PLL2DIVR_DIVR
#define BF_RCC_PLL2DIVR_DIVR_V(e)   BF_RCC_PLL2DIVR_DIVR(BV_RCC_PLL2DIVR_DIVR__##e)
#define BFM_RCC_PLL2DIVR_DIVR_V(v)  BM_RCC_PLL2DIVR_DIVR
#define BP_RCC_PLL2DIVR_DIVQ        16
#define BM_RCC_PLL2DIVR_DIVQ        0x7f0000
#define BF_RCC_PLL2DIVR_DIVQ(v)     (((v) & 0x7f) << 16)
#define BFM_RCC_PLL2DIVR_DIVQ(v)    BM_RCC_PLL2DIVR_DIVQ
#define BF_RCC_PLL2DIVR_DIVQ_V(e)   BF_RCC_PLL2DIVR_DIVQ(BV_RCC_PLL2DIVR_DIVQ__##e)
#define BFM_RCC_PLL2DIVR_DIVQ_V(v)  BM_RCC_PLL2DIVR_DIVQ
#define BP_RCC_PLL2DIVR_DIVP        9
#define BM_RCC_PLL2DIVR_DIVP        0xfe00
#define BF_RCC_PLL2DIVR_DIVP(v)     (((v) & 0x7f) << 9)
#define BFM_RCC_PLL2DIVR_DIVP(v)    BM_RCC_PLL2DIVR_DIVP
#define BF_RCC_PLL2DIVR_DIVP_V(e)   BF_RCC_PLL2DIVR_DIVP(BV_RCC_PLL2DIVR_DIVP__##e)
#define BFM_RCC_PLL2DIVR_DIVP_V(v)  BM_RCC_PLL2DIVR_DIVP
#define BP_RCC_PLL2DIVR_DIVN        0
#define BM_RCC_PLL2DIVR_DIVN        0x1ff
#define BF_RCC_PLL2DIVR_DIVN(v)     (((v) & 0x1ff) << 0)
#define BFM_RCC_PLL2DIVR_DIVN(v)    BM_RCC_PLL2DIVR_DIVN
#define BF_RCC_PLL2DIVR_DIVN_V(e)   BF_RCC_PLL2DIVR_DIVN(BV_RCC_PLL2DIVR_DIVN__##e)
#define BFM_RCC_PLL2DIVR_DIVN_V(v)  BM_RCC_PLL2DIVR_DIVN

#define REG_RCC_PLL3DIVR            st_reg(RCC_PLL3DIVR)
#define STA_RCC_PLL3DIVR            (0x58024400 + 0x40)
#define STO_RCC_PLL3DIVR            (0x40)
#define STT_RCC_PLL3DIVR            STIO_32_RW
#define STN_RCC_PLL3DIVR            RCC_PLL3DIVR
#define BP_RCC_PLL3DIVR_DIVR        24
#define BM_RCC_PLL3DIVR_DIVR        0x7f000000
#define BF_RCC_PLL3DIVR_DIVR(v)     (((v) & 0x7f) << 24)
#define BFM_RCC_PLL3DIVR_DIVR(v)    BM_RCC_PLL3DIVR_DIVR
#define BF_RCC_PLL3DIVR_DIVR_V(e)   BF_RCC_PLL3DIVR_DIVR(BV_RCC_PLL3DIVR_DIVR__##e)
#define BFM_RCC_PLL3DIVR_DIVR_V(v)  BM_RCC_PLL3DIVR_DIVR
#define BP_RCC_PLL3DIVR_DIVQ        16
#define BM_RCC_PLL3DIVR_DIVQ        0x7f0000
#define BF_RCC_PLL3DIVR_DIVQ(v)     (((v) & 0x7f) << 16)
#define BFM_RCC_PLL3DIVR_DIVQ(v)    BM_RCC_PLL3DIVR_DIVQ
#define BF_RCC_PLL3DIVR_DIVQ_V(e)   BF_RCC_PLL3DIVR_DIVQ(BV_RCC_PLL3DIVR_DIVQ__##e)
#define BFM_RCC_PLL3DIVR_DIVQ_V(v)  BM_RCC_PLL3DIVR_DIVQ
#define BP_RCC_PLL3DIVR_DIVP        9
#define BM_RCC_PLL3DIVR_DIVP        0xfe00
#define BF_RCC_PLL3DIVR_DIVP(v)     (((v) & 0x7f) << 9)
#define BFM_RCC_PLL3DIVR_DIVP(v)    BM_RCC_PLL3DIVR_DIVP
#define BF_RCC_PLL3DIVR_DIVP_V(e)   BF_RCC_PLL3DIVR_DIVP(BV_RCC_PLL3DIVR_DIVP__##e)
#define BFM_RCC_PLL3DIVR_DIVP_V(v)  BM_RCC_PLL3DIVR_DIVP
#define BP_RCC_PLL3DIVR_DIVN        0
#define BM_RCC_PLL3DIVR_DIVN        0x1ff
#define BF_RCC_PLL3DIVR_DIVN(v)     (((v) & 0x1ff) << 0)
#define BFM_RCC_PLL3DIVR_DIVN(v)    BM_RCC_PLL3DIVR_DIVN
#define BF_RCC_PLL3DIVR_DIVN_V(e)   BF_RCC_PLL3DIVR_DIVN(BV_RCC_PLL3DIVR_DIVN__##e)
#define BFM_RCC_PLL3DIVR_DIVN_V(v)  BM_RCC_PLL3DIVR_DIVN

#define REG_RCC_PLL1FRACR               st_reg(RCC_PLL1FRACR)
#define STA_RCC_PLL1FRACR               (0x58024400 + 0x34)
#define STO_RCC_PLL1FRACR               (0x34)
#define STT_RCC_PLL1FRACR               STIO_32_RW
#define STN_RCC_PLL1FRACR               RCC_PLL1FRACR
#define BP_RCC_PLL1FRACR_FRACN          3
#define BM_RCC_PLL1FRACR_FRACN          0xfff8
#define BF_RCC_PLL1FRACR_FRACN(v)       (((v) & 0x1fff) << 3)
#define BFM_RCC_PLL1FRACR_FRACN(v)      BM_RCC_PLL1FRACR_FRACN
#define BF_RCC_PLL1FRACR_FRACN_V(e)     BF_RCC_PLL1FRACR_FRACN(BV_RCC_PLL1FRACR_FRACN__##e)
#define BFM_RCC_PLL1FRACR_FRACN_V(v)    BM_RCC_PLL1FRACR_FRACN

#define REG_RCC_PLL2FRACR               st_reg(RCC_PLL2FRACR)
#define STA_RCC_PLL2FRACR               (0x58024400 + 0x3c)
#define STO_RCC_PLL2FRACR               (0x3c)
#define STT_RCC_PLL2FRACR               STIO_32_RW
#define STN_RCC_PLL2FRACR               RCC_PLL2FRACR
#define BP_RCC_PLL2FRACR_FRACN          3
#define BM_RCC_PLL2FRACR_FRACN          0xfff8
#define BF_RCC_PLL2FRACR_FRACN(v)       (((v) & 0x1fff) << 3)
#define BFM_RCC_PLL2FRACR_FRACN(v)      BM_RCC_PLL2FRACR_FRACN
#define BF_RCC_PLL2FRACR_FRACN_V(e)     BF_RCC_PLL2FRACR_FRACN(BV_RCC_PLL2FRACR_FRACN__##e)
#define BFM_RCC_PLL2FRACR_FRACN_V(v)    BM_RCC_PLL2FRACR_FRACN

#define REG_RCC_PLL3FRACR               st_reg(RCC_PLL3FRACR)
#define STA_RCC_PLL3FRACR               (0x58024400 + 0x44)
#define STO_RCC_PLL3FRACR               (0x44)
#define STT_RCC_PLL3FRACR               STIO_32_RW
#define STN_RCC_PLL3FRACR               RCC_PLL3FRACR
#define BP_RCC_PLL3FRACR_FRACN          3
#define BM_RCC_PLL3FRACR_FRACN          0xfff8
#define BF_RCC_PLL3FRACR_FRACN(v)       (((v) & 0x1fff) << 3)
#define BFM_RCC_PLL3FRACR_FRACN(v)      BM_RCC_PLL3FRACR_FRACN
#define BF_RCC_PLL3FRACR_FRACN_V(e)     BF_RCC_PLL3FRACR_FRACN(BV_RCC_PLL3FRACR_FRACN__##e)
#define BFM_RCC_PLL3FRACR_FRACN_V(v)    BM_RCC_PLL3FRACR_FRACN

#define REG_RCC_D1CCIPR                 st_reg(RCC_D1CCIPR)
#define STA_RCC_D1CCIPR                 (0x58024400 + 0x4c)
#define STO_RCC_D1CCIPR                 (0x4c)
#define STT_RCC_D1CCIPR                 STIO_32_RW
#define STN_RCC_D1CCIPR                 RCC_D1CCIPR
#define BP_RCC_D1CCIPR_CKPERSEL         28
#define BM_RCC_D1CCIPR_CKPERSEL         0x30000000
#define BV_RCC_D1CCIPR_CKPERSEL__HSI    0x0
#define BV_RCC_D1CCIPR_CKPERSEL__CSI    0x1
#define BV_RCC_D1CCIPR_CKPERSEL__HSE    0x2
#define BF_RCC_D1CCIPR_CKPERSEL(v)      (((v) & 0x3) << 28)
#define BFM_RCC_D1CCIPR_CKPERSEL(v)     BM_RCC_D1CCIPR_CKPERSEL
#define BF_RCC_D1CCIPR_CKPERSEL_V(e)    BF_RCC_D1CCIPR_CKPERSEL(BV_RCC_D1CCIPR_CKPERSEL__##e)
#define BFM_RCC_D1CCIPR_CKPERSEL_V(v)   BM_RCC_D1CCIPR_CKPERSEL
#define BP_RCC_D1CCIPR_QSPISEL          4
#define BM_RCC_D1CCIPR_QSPISEL          0x30
#define BV_RCC_D1CCIPR_QSPISEL__AHB     0x0
#define BV_RCC_D1CCIPR_QSPISEL__PLL1Q   0x1
#define BV_RCC_D1CCIPR_QSPISEL__PLL2R   0x2
#define BV_RCC_D1CCIPR_QSPISEL__PER     0x3
#define BF_RCC_D1CCIPR_QSPISEL(v)       (((v) & 0x3) << 4)
#define BFM_RCC_D1CCIPR_QSPISEL(v)      BM_RCC_D1CCIPR_QSPISEL
#define BF_RCC_D1CCIPR_QSPISEL_V(e)     BF_RCC_D1CCIPR_QSPISEL(BV_RCC_D1CCIPR_QSPISEL__##e)
#define BFM_RCC_D1CCIPR_QSPISEL_V(v)    BM_RCC_D1CCIPR_QSPISEL
#define BP_RCC_D1CCIPR_FMCSEL           0
#define BM_RCC_D1CCIPR_FMCSEL           0x3
#define BV_RCC_D1CCIPR_FMCSEL__AHB      0x0
#define BV_RCC_D1CCIPR_FMCSEL__PLL1Q    0x1
#define BV_RCC_D1CCIPR_FMCSEL__PLL2R    0x2
#define BV_RCC_D1CCIPR_FMCSEL__PER      0x3
#define BF_RCC_D1CCIPR_FMCSEL(v)        (((v) & 0x3) << 0)
#define BFM_RCC_D1CCIPR_FMCSEL(v)       BM_RCC_D1CCIPR_FMCSEL
#define BF_RCC_D1CCIPR_FMCSEL_V(e)      BF_RCC_D1CCIPR_FMCSEL(BV_RCC_D1CCIPR_FMCSEL__##e)
#define BFM_RCC_D1CCIPR_FMCSEL_V(v)     BM_RCC_D1CCIPR_FMCSEL
#define BP_RCC_D1CCIPR_SDMMCSEL         16
#define BM_RCC_D1CCIPR_SDMMCSEL         0x10000
#define BV_RCC_D1CCIPR_SDMMCSEL__PLL1Q  0x0
#define BV_RCC_D1CCIPR_SDMMCSEL__PLL2R  0x1
#define BF_RCC_D1CCIPR_SDMMCSEL(v)      (((v) & 0x1) << 16)
#define BFM_RCC_D1CCIPR_SDMMCSEL(v)     BM_RCC_D1CCIPR_SDMMCSEL
#define BF_RCC_D1CCIPR_SDMMCSEL_V(e)    BF_RCC_D1CCIPR_SDMMCSEL(BV_RCC_D1CCIPR_SDMMCSEL__##e)
#define BFM_RCC_D1CCIPR_SDMMCSEL_V(v)   BM_RCC_D1CCIPR_SDMMCSEL

#define REG_RCC_D2CCIP1R                    st_reg(RCC_D2CCIP1R)
#define STA_RCC_D2CCIP1R                    (0x58024400 + 0x50)
#define STO_RCC_D2CCIP1R                    (0x50)
#define STT_RCC_D2CCIP1R                    STIO_32_RW
#define STN_RCC_D2CCIP1R                    RCC_D2CCIP1R
#define BP_RCC_D2CCIP1R_FDCANSEL            28
#define BM_RCC_D2CCIP1R_FDCANSEL            0x30000000
#define BV_RCC_D2CCIP1R_FDCANSEL__HSE       0x0
#define BV_RCC_D2CCIP1R_FDCANSEL__PLL1Q     0x1
#define BV_RCC_D2CCIP1R_FDCANSEL__PLL2Q     0x1
#define BF_RCC_D2CCIP1R_FDCANSEL(v)         (((v) & 0x3) << 28)
#define BFM_RCC_D2CCIP1R_FDCANSEL(v)        BM_RCC_D2CCIP1R_FDCANSEL
#define BF_RCC_D2CCIP1R_FDCANSEL_V(e)       BF_RCC_D2CCIP1R_FDCANSEL(BV_RCC_D2CCIP1R_FDCANSEL__##e)
#define BFM_RCC_D2CCIP1R_FDCANSEL_V(v)      BM_RCC_D2CCIP1R_FDCANSEL
#define BP_RCC_D2CCIP1R_SPDIFSEL            20
#define BM_RCC_D2CCIP1R_SPDIFSEL            0x300000
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL1Q     0x0
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL2R     0x1
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL3R     0x2
#define BV_RCC_D2CCIP1R_SPDIFSEL__HSI       0x3
#define BF_RCC_D2CCIP1R_SPDIFSEL(v)         (((v) & 0x3) << 20)
#define BFM_RCC_D2CCIP1R_SPDIFSEL(v)        BM_RCC_D2CCIP1R_SPDIFSEL
#define BF_RCC_D2CCIP1R_SPDIFSEL_V(e)       BF_RCC_D2CCIP1R_SPDIFSEL(BV_RCC_D2CCIP1R_SPDIFSEL__##e)
#define BFM_RCC_D2CCIP1R_SPDIFSEL_V(v)      BM_RCC_D2CCIP1R_SPDIFSEL
#define BP_RCC_D2CCIP1R_SPI45SEL            16
#define BM_RCC_D2CCIP1R_SPI45SEL            0x70000
#define BV_RCC_D2CCIP1R_SPI45SEL__APB2      0x0
#define BV_RCC_D2CCIP1R_SPI45SEL__PLL2Q     0x1
#define BV_RCC_D2CCIP1R_SPI45SEL__PLL3Q     0x2
#define BV_RCC_D2CCIP1R_SPI45SEL__HSI       0x3
#define BV_RCC_D2CCIP1R_SPI45SEL__CSI       0x4
#define BV_RCC_D2CCIP1R_SPI45SEL__HSE       0x5
#define BF_RCC_D2CCIP1R_SPI45SEL(v)         (((v) & 0x7) << 16)
#define BFM_RCC_D2CCIP1R_SPI45SEL(v)        BM_RCC_D2CCIP1R_SPI45SEL
#define BF_RCC_D2CCIP1R_SPI45SEL_V(e)       BF_RCC_D2CCIP1R_SPI45SEL(BV_RCC_D2CCIP1R_SPI45SEL__##e)
#define BFM_RCC_D2CCIP1R_SPI45SEL_V(v)      BM_RCC_D2CCIP1R_SPI45SEL
#define BP_RCC_D2CCIP1R_SPI123SEL           12
#define BM_RCC_D2CCIP1R_SPI123SEL           0x7000
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL1Q    0x0
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL2P    0x1
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL3P    0x2
#define BV_RCC_D2CCIP1R_SPI123SEL__I2SCKIN  0x3
#define BV_RCC_D2CCIP1R_SPI123SEL__PER      0x4
#define BF_RCC_D2CCIP1R_SPI123SEL(v)        (((v) & 0x7) << 12)
#define BFM_RCC_D2CCIP1R_SPI123SEL(v)       BM_RCC_D2CCIP1R_SPI123SEL
#define BF_RCC_D2CCIP1R_SPI123SEL_V(e)      BF_RCC_D2CCIP1R_SPI123SEL(BV_RCC_D2CCIP1R_SPI123SEL__##e)
#define BFM_RCC_D2CCIP1R_SPI123SEL_V(v)     BM_RCC_D2CCIP1R_SPI123SEL
#define BP_RCC_D2CCIP1R_SAI23SEL            6
#define BM_RCC_D2CCIP1R_SAI23SEL            0x1c0
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL1Q     0x0
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL2P     0x1
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL3P     0x2
#define BV_RCC_D2CCIP1R_SAI23SEL__I2SCKIN   0x4
#define BV_RCC_D2CCIP1R_SAI23SEL__PER       0x4
#define BF_RCC_D2CCIP1R_SAI23SEL(v)         (((v) & 0x7) << 6)
#define BFM_RCC_D2CCIP1R_SAI23SEL(v)        BM_RCC_D2CCIP1R_SAI23SEL
#define BF_RCC_D2CCIP1R_SAI23SEL_V(e)       BF_RCC_D2CCIP1R_SAI23SEL(BV_RCC_D2CCIP1R_SAI23SEL__##e)
#define BFM_RCC_D2CCIP1R_SAI23SEL_V(v)      BM_RCC_D2CCIP1R_SAI23SEL
#define BP_RCC_D2CCIP1R_SAI1SEL             0
#define BM_RCC_D2CCIP1R_SAI1SEL             0x7
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL1Q      0x0
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL2P      0x1
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL3P      0x2
#define BV_RCC_D2CCIP1R_SAI1SEL__I2SCKIN    0x4
#define BV_RCC_D2CCIP1R_SAI1SEL__PER        0x4
#define BF_RCC_D2CCIP1R_SAI1SEL(v)          (((v) & 0x7) << 0)
#define BFM_RCC_D2CCIP1R_SAI1SEL(v)         BM_RCC_D2CCIP1R_SAI1SEL
#define BF_RCC_D2CCIP1R_SAI1SEL_V(e)        BF_RCC_D2CCIP1R_SAI1SEL(BV_RCC_D2CCIP1R_SAI1SEL__##e)
#define BFM_RCC_D2CCIP1R_SAI1SEL_V(v)       BM_RCC_D2CCIP1R_SAI1SEL
#define BP_RCC_D2CCIP1R_SWPSEL              31
#define BM_RCC_D2CCIP1R_SWPSEL              0x80000000
#define BV_RCC_D2CCIP1R_SWPSEL__APB1        0x0
#define BV_RCC_D2CCIP1R_SWPSEL__HSI         0x1
#define BF_RCC_D2CCIP1R_SWPSEL(v)           (((v) & 0x1) << 31)
#define BFM_RCC_D2CCIP1R_SWPSEL(v)          BM_RCC_D2CCIP1R_SWPSEL
#define BF_RCC_D2CCIP1R_SWPSEL_V(e)         BF_RCC_D2CCIP1R_SWPSEL(BV_RCC_D2CCIP1R_SWPSEL__##e)
#define BFM_RCC_D2CCIP1R_SWPSEL_V(v)        BM_RCC_D2CCIP1R_SWPSEL
#define BP_RCC_D2CCIP1R_DFSDM1SEL           24
#define BM_RCC_D2CCIP1R_DFSDM1SEL           0x1000000
#define BV_RCC_D2CCIP1R_DFSDM1SEL__APB2     0x0
#define BV_RCC_D2CCIP1R_DFSDM1SEL__SYSCLK   0x1
#define BF_RCC_D2CCIP1R_DFSDM1SEL(v)        (((v) & 0x1) << 24)
#define BFM_RCC_D2CCIP1R_DFSDM1SEL(v)       BM_RCC_D2CCIP1R_DFSDM1SEL
#define BF_RCC_D2CCIP1R_DFSDM1SEL_V(e)      BF_RCC_D2CCIP1R_DFSDM1SEL(BV_RCC_D2CCIP1R_DFSDM1SEL__##e)
#define BFM_RCC_D2CCIP1R_DFSDM1SEL_V(v)     BM_RCC_D2CCIP1R_DFSDM1SEL

#define REG_RCC_D2CCIP2R                        st_reg(RCC_D2CCIP2R)
#define STA_RCC_D2CCIP2R                        (0x58024400 + 0x54)
#define STO_RCC_D2CCIP2R                        (0x54)
#define STT_RCC_D2CCIP2R                        STIO_32_RW
#define STN_RCC_D2CCIP2R                        RCC_D2CCIP2R
#define BP_RCC_D2CCIP2R_LPTIM1SEL               28
#define BM_RCC_D2CCIP2R_LPTIM1SEL               0x70000000
#define BV_RCC_D2CCIP2R_LPTIM1SEL__APB1         0x0
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL2P        0x1
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL3R        0x2
#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSE          0x3
#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSI          0x4
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PER          0x5
#define BF_RCC_D2CCIP2R_LPTIM1SEL(v)            (((v) & 0x7) << 28)
#define BFM_RCC_D2CCIP2R_LPTIM1SEL(v)           BM_RCC_D2CCIP2R_LPTIM1SEL
#define BF_RCC_D2CCIP2R_LPTIM1SEL_V(e)          BF_RCC_D2CCIP2R_LPTIM1SEL(BV_RCC_D2CCIP2R_LPTIM1SEL__##e)
#define BFM_RCC_D2CCIP2R_LPTIM1SEL_V(v)         BM_RCC_D2CCIP2R_LPTIM1SEL
#define BP_RCC_D2CCIP2R_CECSEL                  22
#define BM_RCC_D2CCIP2R_CECSEL                  0xc00000
#define BV_RCC_D2CCIP2R_CECSEL__LSE             0x0
#define BV_RCC_D2CCIP2R_CECSEL__LSI             0x1
#define BV_RCC_D2CCIP2R_CECSEL__CSI             0x2
#define BF_RCC_D2CCIP2R_CECSEL(v)               (((v) & 0x3) << 22)
#define BFM_RCC_D2CCIP2R_CECSEL(v)              BM_RCC_D2CCIP2R_CECSEL
#define BF_RCC_D2CCIP2R_CECSEL_V(e)             BF_RCC_D2CCIP2R_CECSEL(BV_RCC_D2CCIP2R_CECSEL__##e)
#define BFM_RCC_D2CCIP2R_CECSEL_V(v)            BM_RCC_D2CCIP2R_CECSEL
#define BP_RCC_D2CCIP2R_USBSEL                  20
#define BM_RCC_D2CCIP2R_USBSEL                  0x300000
#define BV_RCC_D2CCIP2R_USBSEL__DISABLE         0x0
#define BV_RCC_D2CCIP2R_USBSEL__PLL1Q           0x1
#define BV_RCC_D2CCIP2R_USBSEL__PLL3Q           0x2
#define BV_RCC_D2CCIP2R_USBSEL__HSI48           0x3
#define BF_RCC_D2CCIP2R_USBSEL(v)               (((v) & 0x3) << 20)
#define BFM_RCC_D2CCIP2R_USBSEL(v)              BM_RCC_D2CCIP2R_USBSEL
#define BF_RCC_D2CCIP2R_USBSEL_V(e)             BF_RCC_D2CCIP2R_USBSEL(BV_RCC_D2CCIP2R_USBSEL__##e)
#define BFM_RCC_D2CCIP2R_USBSEL_V(v)            BM_RCC_D2CCIP2R_USBSEL
#define BP_RCC_D2CCIP2R_I2C123SEL               12
#define BM_RCC_D2CCIP2R_I2C123SEL               0x3000
#define BV_RCC_D2CCIP2R_I2C123SEL__APB1         0x0
#define BV_RCC_D2CCIP2R_I2C123SEL__PLL3R        0x1
#define BV_RCC_D2CCIP2R_I2C123SEL__HSI          0x2
#define BV_RCC_D2CCIP2R_I2C123SEL__CSI          0x3
#define BF_RCC_D2CCIP2R_I2C123SEL(v)            (((v) & 0x3) << 12)
#define BFM_RCC_D2CCIP2R_I2C123SEL(v)           BM_RCC_D2CCIP2R_I2C123SEL
#define BF_RCC_D2CCIP2R_I2C123SEL_V(e)          BF_RCC_D2CCIP2R_I2C123SEL(BV_RCC_D2CCIP2R_I2C123SEL__##e)
#define BFM_RCC_D2CCIP2R_I2C123SEL_V(v)         BM_RCC_D2CCIP2R_I2C123SEL
#define BP_RCC_D2CCIP2R_RNGSEL                  8
#define BM_RCC_D2CCIP2R_RNGSEL                  0x300
#define BV_RCC_D2CCIP2R_RNGSEL__HSI             0x0
#define BV_RCC_D2CCIP2R_RNGSEL__PLL1Q           0x1
#define BV_RCC_D2CCIP2R_RNGSEL__LSE             0x2
#define BV_RCC_D2CCIP2R_RNGSEL__LSI             0x3
#define BF_RCC_D2CCIP2R_RNGSEL(v)               (((v) & 0x3) << 8)
#define BFM_RCC_D2CCIP2R_RNGSEL(v)              BM_RCC_D2CCIP2R_RNGSEL
#define BF_RCC_D2CCIP2R_RNGSEL_V(e)             BF_RCC_D2CCIP2R_RNGSEL(BV_RCC_D2CCIP2R_RNGSEL__##e)
#define BFM_RCC_D2CCIP2R_RNGSEL_V(v)            BM_RCC_D2CCIP2R_RNGSEL
#define BP_RCC_D2CCIP2R_USART16SEL              3
#define BM_RCC_D2CCIP2R_USART16SEL              0x38
#define BV_RCC_D2CCIP2R_USART16SEL__APB2        0x0
#define BV_RCC_D2CCIP2R_USART16SEL__PLL2Q       0x1
#define BV_RCC_D2CCIP2R_USART16SEL__PLL3Q       0x2
#define BV_RCC_D2CCIP2R_USART16SEL__HSI         0x3
#define BV_RCC_D2CCIP2R_USART16SEL__CSI         0x4
#define BV_RCC_D2CCIP2R_USART16SEL__LSE         0x5
#define BF_RCC_D2CCIP2R_USART16SEL(v)           (((v) & 0x7) << 3)
#define BFM_RCC_D2CCIP2R_USART16SEL(v)          BM_RCC_D2CCIP2R_USART16SEL
#define BF_RCC_D2CCIP2R_USART16SEL_V(e)         BF_RCC_D2CCIP2R_USART16SEL(BV_RCC_D2CCIP2R_USART16SEL__##e)
#define BFM_RCC_D2CCIP2R_USART16SEL_V(v)        BM_RCC_D2CCIP2R_USART16SEL
#define BP_RCC_D2CCIP2R_USART234578SEL          0
#define BM_RCC_D2CCIP2R_USART234578SEL          0x7
#define BV_RCC_D2CCIP2R_USART234578SEL__APB1    0x0
#define BV_RCC_D2CCIP2R_USART234578SEL__PLL2Q   0x1
#define BV_RCC_D2CCIP2R_USART234578SEL__PLL3Q   0x2
#define BV_RCC_D2CCIP2R_USART234578SEL__HSI     0x3
#define BV_RCC_D2CCIP2R_USART234578SEL__CSI     0x4
#define BV_RCC_D2CCIP2R_USART234578SEL__LSE     0x5
#define BF_RCC_D2CCIP2R_USART234578SEL(v)       (((v) & 0x7) << 0)
#define BFM_RCC_D2CCIP2R_USART234578SEL(v)      BM_RCC_D2CCIP2R_USART234578SEL
#define BF_RCC_D2CCIP2R_USART234578SEL_V(e)     BF_RCC_D2CCIP2R_USART234578SEL(BV_RCC_D2CCIP2R_USART234578SEL__##e)
#define BFM_RCC_D2CCIP2R_USART234578SEL_V(v)    BM_RCC_D2CCIP2R_USART234578SEL

#define REG_RCC_D3CCIPR                     st_reg(RCC_D3CCIPR)
#define STA_RCC_D3CCIPR                     (0x58024400 + 0x58)
#define STO_RCC_D3CCIPR                     (0x58)
#define STT_RCC_D3CCIPR                     STIO_32_RW
#define STN_RCC_D3CCIPR                     RCC_D3CCIPR
#define BP_RCC_D3CCIPR_SPI6SEL              28
#define BM_RCC_D3CCIPR_SPI6SEL              0x70000000
#define BV_RCC_D3CCIPR_SPI6SEL__APB4        0x0
#define BV_RCC_D3CCIPR_SPI6SEL__PLL2Q       0x1
#define BV_RCC_D3CCIPR_SPI6SEL__PLL3Q       0x2
#define BV_RCC_D3CCIPR_SPI6SEL__HSI         0x3
#define BV_RCC_D3CCIPR_SPI6SEL__CSI         0x4
#define BV_RCC_D3CCIPR_SPI6SEL__HSE         0x5
#define BF_RCC_D3CCIPR_SPI6SEL(v)           (((v) & 0x7) << 28)
#define BFM_RCC_D3CCIPR_SPI6SEL(v)          BM_RCC_D3CCIPR_SPI6SEL
#define BF_RCC_D3CCIPR_SPI6SEL_V(e)         BF_RCC_D3CCIPR_SPI6SEL(BV_RCC_D3CCIPR_SPI6SEL__##e)
#define BFM_RCC_D3CCIPR_SPI6SEL_V(v)        BM_RCC_D3CCIPR_SPI6SEL
#define BP_RCC_D3CCIPR_SAI4BSEL             24
#define BM_RCC_D3CCIPR_SAI4BSEL             0x7000000
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL1Q      0x0
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL2P      0x1
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL3P      0x2
#define BV_RCC_D3CCIPR_SAI4BSEL__I2S_CKIN   0x3
#define BV_RCC_D3CCIPR_SAI4BSEL__PER        0x4
#define BF_RCC_D3CCIPR_SAI4BSEL(v)          (((v) & 0x7) << 24)
#define BFM_RCC_D3CCIPR_SAI4BSEL(v)         BM_RCC_D3CCIPR_SAI4BSEL
#define BF_RCC_D3CCIPR_SAI4BSEL_V(e)        BF_RCC_D3CCIPR_SAI4BSEL(BV_RCC_D3CCIPR_SAI4BSEL__##e)
#define BFM_RCC_D3CCIPR_SAI4BSEL_V(v)       BM_RCC_D3CCIPR_SAI4BSEL
#define BP_RCC_D3CCIPR_SAI4ASEL             21
#define BM_RCC_D3CCIPR_SAI4ASEL             0xe00000
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL1Q      0x0
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL2P      0x1
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL3P      0x2
#define BV_RCC_D3CCIPR_SAI4ASEL__I2S_CKIN   0x3
#define BV_RCC_D3CCIPR_SAI4ASEL__PER        0x4
#define BF_RCC_D3CCIPR_SAI4ASEL(v)          (((v) & 0x7) << 21)
#define BFM_RCC_D3CCIPR_SAI4ASEL(v)         BM_RCC_D3CCIPR_SAI4ASEL
#define BF_RCC_D3CCIPR_SAI4ASEL_V(e)        BF_RCC_D3CCIPR_SAI4ASEL(BV_RCC_D3CCIPR_SAI4ASEL__##e)
#define BFM_RCC_D3CCIPR_SAI4ASEL_V(v)       BM_RCC_D3CCIPR_SAI4ASEL
#define BP_RCC_D3CCIPR_ADCSEL               16
#define BM_RCC_D3CCIPR_ADCSEL               0x30000
#define BV_RCC_D3CCIPR_ADCSEL__PLL2P        0x0
#define BV_RCC_D3CCIPR_ADCSEL__PLL3R        0x1
#define BV_RCC_D3CCIPR_ADCSEL__PER          0x2
#define BF_RCC_D3CCIPR_ADCSEL(v)            (((v) & 0x3) << 16)
#define BFM_RCC_D3CCIPR_ADCSEL(v)           BM_RCC_D3CCIPR_ADCSEL
#define BF_RCC_D3CCIPR_ADCSEL_V(e)          BF_RCC_D3CCIPR_ADCSEL(BV_RCC_D3CCIPR_ADCSEL__##e)
#define BFM_RCC_D3CCIPR_ADCSEL_V(v)         BM_RCC_D3CCIPR_ADCSEL
#define BP_RCC_D3CCIPR_LPTIM345SEL          13
#define BM_RCC_D3CCIPR_LPTIM345SEL          0xe000
#define BV_RCC_D3CCIPR_LPTIM345SEL__APB4    0x0
#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL2P   0x1
#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL3R   0x2
#define BV_RCC_D3CCIPR_LPTIM345SEL__LSE     0x3
#define BV_RCC_D3CCIPR_LPTIM345SEL__LSI     0x4
#define BV_RCC_D3CCIPR_LPTIM345SEL__PER     0x5
#define BF_RCC_D3CCIPR_LPTIM345SEL(v)       (((v) & 0x7) << 13)
#define BFM_RCC_D3CCIPR_LPTIM345SEL(v)      BM_RCC_D3CCIPR_LPTIM345SEL
#define BF_RCC_D3CCIPR_LPTIM345SEL_V(e)     BF_RCC_D3CCIPR_LPTIM345SEL(BV_RCC_D3CCIPR_LPTIM345SEL__##e)
#define BFM_RCC_D3CCIPR_LPTIM345SEL_V(v)    BM_RCC_D3CCIPR_LPTIM345SEL
#define BP_RCC_D3CCIPR_LPTIM2SEL            10
#define BM_RCC_D3CCIPR_LPTIM2SEL            0x1c00
#define BV_RCC_D3CCIPR_LPTIM2SEL__APB4      0x0
#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL2P     0x1
#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL3R     0x2
#define BV_RCC_D3CCIPR_LPTIM2SEL__LSE       0x3
#define BV_RCC_D3CCIPR_LPTIM2SEL__LSI       0x4
#define BV_RCC_D3CCIPR_LPTIM2SEL__PER       0x5
#define BF_RCC_D3CCIPR_LPTIM2SEL(v)         (((v) & 0x7) << 10)
#define BFM_RCC_D3CCIPR_LPTIM2SEL(v)        BM_RCC_D3CCIPR_LPTIM2SEL
#define BF_RCC_D3CCIPR_LPTIM2SEL_V(e)       BF_RCC_D3CCIPR_LPTIM2SEL(BV_RCC_D3CCIPR_LPTIM2SEL__##e)
#define BFM_RCC_D3CCIPR_LPTIM2SEL_V(v)      BM_RCC_D3CCIPR_LPTIM2SEL
#define BP_RCC_D3CCIPR_I2C4SEL              8
#define BM_RCC_D3CCIPR_I2C4SEL              0x300
#define BV_RCC_D3CCIPR_I2C4SEL__APB4        0x0
#define BV_RCC_D3CCIPR_I2C4SEL__PLL3R       0x1
#define BV_RCC_D3CCIPR_I2C4SEL__HSI         0x2
#define BV_RCC_D3CCIPR_I2C4SEL__CSI         0x3
#define BF_RCC_D3CCIPR_I2C4SEL(v)           (((v) & 0x3) << 8)
#define BFM_RCC_D3CCIPR_I2C4SEL(v)          BM_RCC_D3CCIPR_I2C4SEL
#define BF_RCC_D3CCIPR_I2C4SEL_V(e)         BF_RCC_D3CCIPR_I2C4SEL(BV_RCC_D3CCIPR_I2C4SEL__##e)
#define BFM_RCC_D3CCIPR_I2C4SEL_V(v)        BM_RCC_D3CCIPR_I2C4SEL
#define BP_RCC_D3CCIPR_LPUART1SEL           0
#define BM_RCC_D3CCIPR_LPUART1SEL           0x7
#define BV_RCC_D3CCIPR_LPUART1SEL__APB4     0x0
#define BV_RCC_D3CCIPR_LPUART1SEL__PLL2Q    0x1
#define BV_RCC_D3CCIPR_LPUART1SEL__PLL3Q    0x2
#define BV_RCC_D3CCIPR_LPUART1SEL__HSI      0x3
#define BV_RCC_D3CCIPR_LPUART1SEL__CSI      0x4
#define BV_RCC_D3CCIPR_LPUART1SEL__LSE      0x5
#define BF_RCC_D3CCIPR_LPUART1SEL(v)        (((v) & 0x7) << 0)
#define BFM_RCC_D3CCIPR_LPUART1SEL(v)       BM_RCC_D3CCIPR_LPUART1SEL
#define BF_RCC_D3CCIPR_LPUART1SEL_V(e)      BF_RCC_D3CCIPR_LPUART1SEL(BV_RCC_D3CCIPR_LPUART1SEL__##e)
#define BFM_RCC_D3CCIPR_LPUART1SEL_V(v)     BM_RCC_D3CCIPR_LPUART1SEL

#define REG_RCC_BDCR                    st_reg(RCC_BDCR)
#define STA_RCC_BDCR                    (0x58024400 + 0x70)
#define STO_RCC_BDCR                    (0x70)
#define STT_RCC_BDCR                    STIO_32_RW
#define STN_RCC_BDCR                    RCC_BDCR
#define BP_RCC_BDCR_RTCSEL              8
#define BM_RCC_BDCR_RTCSEL              0x300
#define BV_RCC_BDCR_RTCSEL__NONE        0x0
#define BV_RCC_BDCR_RTCSEL__LSE         0x1
#define BV_RCC_BDCR_RTCSEL__LSI         0x2
#define BV_RCC_BDCR_RTCSEL__HSE         0x3
#define BF_RCC_BDCR_RTCSEL(v)           (((v) & 0x3) << 8)
#define BFM_RCC_BDCR_RTCSEL(v)          BM_RCC_BDCR_RTCSEL
#define BF_RCC_BDCR_RTCSEL_V(e)         BF_RCC_BDCR_RTCSEL(BV_RCC_BDCR_RTCSEL__##e)
#define BFM_RCC_BDCR_RTCSEL_V(v)        BM_RCC_BDCR_RTCSEL
#define BP_RCC_BDCR_LSEDRV              3
#define BM_RCC_BDCR_LSEDRV              0x18
#define BV_RCC_BDCR_LSEDRV__LOW         0x0
#define BV_RCC_BDCR_LSEDRV__MED_LOW     0x1
#define BV_RCC_BDCR_LSEDRV__MED_HIGH    0x2
#define BV_RCC_BDCR_LSEDRV__HIGH        0x3
#define BF_RCC_BDCR_LSEDRV(v)           (((v) & 0x3) << 3)
#define BFM_RCC_BDCR_LSEDRV(v)          BM_RCC_BDCR_LSEDRV
#define BF_RCC_BDCR_LSEDRV_V(e)         BF_RCC_BDCR_LSEDRV(BV_RCC_BDCR_LSEDRV__##e)
#define BFM_RCC_BDCR_LSEDRV_V(v)        BM_RCC_BDCR_LSEDRV
#define BP_RCC_BDCR_BDRST               16
#define BM_RCC_BDCR_BDRST               0x10000
#define BF_RCC_BDCR_BDRST(v)            (((v) & 0x1) << 16)
#define BFM_RCC_BDCR_BDRST(v)           BM_RCC_BDCR_BDRST
#define BF_RCC_BDCR_BDRST_V(e)          BF_RCC_BDCR_BDRST(BV_RCC_BDCR_BDRST__##e)
#define BFM_RCC_BDCR_BDRST_V(v)         BM_RCC_BDCR_BDRST
#define BP_RCC_BDCR_RTCEN               15
#define BM_RCC_BDCR_RTCEN               0x8000
#define BF_RCC_BDCR_RTCEN(v)            (((v) & 0x1) << 15)
#define BFM_RCC_BDCR_RTCEN(v)           BM_RCC_BDCR_RTCEN
#define BF_RCC_BDCR_RTCEN_V(e)          BF_RCC_BDCR_RTCEN(BV_RCC_BDCR_RTCEN__##e)
#define BFM_RCC_BDCR_RTCEN_V(v)         BM_RCC_BDCR_RTCEN
#define BP_RCC_BDCR_LSECSSD             6
#define BM_RCC_BDCR_LSECSSD             0x40
#define BF_RCC_BDCR_LSECSSD(v)          (((v) & 0x1) << 6)
#define BFM_RCC_BDCR_LSECSSD(v)         BM_RCC_BDCR_LSECSSD
#define BF_RCC_BDCR_LSECSSD_V(e)        BF_RCC_BDCR_LSECSSD(BV_RCC_BDCR_LSECSSD__##e)
#define BFM_RCC_BDCR_LSECSSD_V(v)       BM_RCC_BDCR_LSECSSD
#define BP_RCC_BDCR_LSECSSON            5
#define BM_RCC_BDCR_LSECSSON            0x20
#define BF_RCC_BDCR_LSECSSON(v)         (((v) & 0x1) << 5)
#define BFM_RCC_BDCR_LSECSSON(v)        BM_RCC_BDCR_LSECSSON
#define BF_RCC_BDCR_LSECSSON_V(e)       BF_RCC_BDCR_LSECSSON(BV_RCC_BDCR_LSECSSON__##e)
#define BFM_RCC_BDCR_LSECSSON_V(v)      BM_RCC_BDCR_LSECSSON
#define BP_RCC_BDCR_LSEBYP              2
#define BM_RCC_BDCR_LSEBYP              0x4
#define BF_RCC_BDCR_LSEBYP(v)           (((v) & 0x1) << 2)
#define BFM_RCC_BDCR_LSEBYP(v)          BM_RCC_BDCR_LSEBYP
#define BF_RCC_BDCR_LSEBYP_V(e)         BF_RCC_BDCR_LSEBYP(BV_RCC_BDCR_LSEBYP__##e)
#define BFM_RCC_BDCR_LSEBYP_V(v)        BM_RCC_BDCR_LSEBYP
#define BP_RCC_BDCR_LSERDY              1
#define BM_RCC_BDCR_LSERDY              0x2
#define BF_RCC_BDCR_LSERDY(v)           (((v) & 0x1) << 1)
#define BFM_RCC_BDCR_LSERDY(v)          BM_RCC_BDCR_LSERDY
#define BF_RCC_BDCR_LSERDY_V(e)         BF_RCC_BDCR_LSERDY(BV_RCC_BDCR_LSERDY__##e)
#define BFM_RCC_BDCR_LSERDY_V(v)        BM_RCC_BDCR_LSERDY
#define BP_RCC_BDCR_LSEON               0
#define BM_RCC_BDCR_LSEON               0x1
#define BF_RCC_BDCR_LSEON(v)            (((v) & 0x1) << 0)
#define BFM_RCC_BDCR_LSEON(v)           BM_RCC_BDCR_LSEON
#define BF_RCC_BDCR_LSEON_V(e)          BF_RCC_BDCR_LSEON(BV_RCC_BDCR_LSEON__##e)
#define BFM_RCC_BDCR_LSEON_V(v)         BM_RCC_BDCR_LSEON

#define REG_RCC_CSR             st_reg(RCC_CSR)
#define STA_RCC_CSR             (0x58024400 + 0x74)
#define STO_RCC_CSR             (0x74)
#define STT_RCC_CSR             STIO_32_RW
#define STN_RCC_CSR             RCC_CSR
#define BP_RCC_CSR_LSIRDY       1
#define BM_RCC_CSR_LSIRDY       0x2
#define BF_RCC_CSR_LSIRDY(v)    (((v) & 0x1) << 1)
#define BFM_RCC_CSR_LSIRDY(v)   BM_RCC_CSR_LSIRDY
#define BF_RCC_CSR_LSIRDY_V(e)  BF_RCC_CSR_LSIRDY(BV_RCC_CSR_LSIRDY__##e)
#define BFM_RCC_CSR_LSIRDY_V(v) BM_RCC_CSR_LSIRDY
#define BP_RCC_CSR_LSION        0
#define BM_RCC_CSR_LSION        0x1
#define BF_RCC_CSR_LSION(v)     (((v) & 0x1) << 0)
#define BFM_RCC_CSR_LSION(v)    BM_RCC_CSR_LSION
#define BF_RCC_CSR_LSION_V(e)   BF_RCC_CSR_LSION(BV_RCC_CSR_LSION__##e)
#define BFM_RCC_CSR_LSION_V(v)  BM_RCC_CSR_LSION

#define REG_RCC_AHB3ENR                 st_reg(RCC_AHB3ENR)
#define STA_RCC_AHB3ENR                 (0x58024400 + 0xd4)
#define STO_RCC_AHB3ENR                 (0xd4)
#define STT_RCC_AHB3ENR                 STIO_32_RW
#define STN_RCC_AHB3ENR                 RCC_AHB3ENR
#define BP_RCC_AHB3ENR_AXISRAMEN        31
#define BM_RCC_AHB3ENR_AXISRAMEN        0x80000000
#define BF_RCC_AHB3ENR_AXISRAMEN(v)     (((v) & 0x1) << 31)
#define BFM_RCC_AHB3ENR_AXISRAMEN(v)    BM_RCC_AHB3ENR_AXISRAMEN
#define BF_RCC_AHB3ENR_AXISRAMEN_V(e)   BF_RCC_AHB3ENR_AXISRAMEN(BV_RCC_AHB3ENR_AXISRAMEN__##e)
#define BFM_RCC_AHB3ENR_AXISRAMEN_V(v)  BM_RCC_AHB3ENR_AXISRAMEN
#define BP_RCC_AHB3ENR_ITCMEN           30
#define BM_RCC_AHB3ENR_ITCMEN           0x40000000
#define BF_RCC_AHB3ENR_ITCMEN(v)        (((v) & 0x1) << 30)
#define BFM_RCC_AHB3ENR_ITCMEN(v)       BM_RCC_AHB3ENR_ITCMEN
#define BF_RCC_AHB3ENR_ITCMEN_V(e)      BF_RCC_AHB3ENR_ITCMEN(BV_RCC_AHB3ENR_ITCMEN__##e)
#define BFM_RCC_AHB3ENR_ITCMEN_V(v)     BM_RCC_AHB3ENR_ITCMEN
#define BP_RCC_AHB3ENR_DTCM2EN          29
#define BM_RCC_AHB3ENR_DTCM2EN          0x20000000
#define BF_RCC_AHB3ENR_DTCM2EN(v)       (((v) & 0x1) << 29)
#define BFM_RCC_AHB3ENR_DTCM2EN(v)      BM_RCC_AHB3ENR_DTCM2EN
#define BF_RCC_AHB3ENR_DTCM2EN_V(e)     BF_RCC_AHB3ENR_DTCM2EN(BV_RCC_AHB3ENR_DTCM2EN__##e)
#define BFM_RCC_AHB3ENR_DTCM2EN_V(v)    BM_RCC_AHB3ENR_DTCM2EN
#define BP_RCC_AHB3ENR_D1DTCM1EN        28
#define BM_RCC_AHB3ENR_D1DTCM1EN        0x10000000
#define BF_RCC_AHB3ENR_D1DTCM1EN(v)     (((v) & 0x1) << 28)
#define BFM_RCC_AHB3ENR_D1DTCM1EN(v)    BM_RCC_AHB3ENR_D1DTCM1EN
#define BF_RCC_AHB3ENR_D1DTCM1EN_V(e)   BF_RCC_AHB3ENR_D1DTCM1EN(BV_RCC_AHB3ENR_D1DTCM1EN__##e)
#define BFM_RCC_AHB3ENR_D1DTCM1EN_V(v)  BM_RCC_AHB3ENR_D1DTCM1EN
#define BP_RCC_AHB3ENR_SDMMC1EN         16
#define BM_RCC_AHB3ENR_SDMMC1EN         0x10000
#define BF_RCC_AHB3ENR_SDMMC1EN(v)      (((v) & 0x1) << 16)
#define BFM_RCC_AHB3ENR_SDMMC1EN(v)     BM_RCC_AHB3ENR_SDMMC1EN
#define BF_RCC_AHB3ENR_SDMMC1EN_V(e)    BF_RCC_AHB3ENR_SDMMC1EN(BV_RCC_AHB3ENR_SDMMC1EN__##e)
#define BFM_RCC_AHB3ENR_SDMMC1EN_V(v)   BM_RCC_AHB3ENR_SDMMC1EN
#define BP_RCC_AHB3ENR_QSPIEN           14
#define BM_RCC_AHB3ENR_QSPIEN           0x4000
#define BF_RCC_AHB3ENR_QSPIEN(v)        (((v) & 0x1) << 14)
#define BFM_RCC_AHB3ENR_QSPIEN(v)       BM_RCC_AHB3ENR_QSPIEN
#define BF_RCC_AHB3ENR_QSPIEN_V(e)      BF_RCC_AHB3ENR_QSPIEN(BV_RCC_AHB3ENR_QSPIEN__##e)
#define BFM_RCC_AHB3ENR_QSPIEN_V(v)     BM_RCC_AHB3ENR_QSPIEN
#define BP_RCC_AHB3ENR_FMCEN            12
#define BM_RCC_AHB3ENR_FMCEN            0x1000
#define BF_RCC_AHB3ENR_FMCEN(v)         (((v) & 0x1) << 12)
#define BFM_RCC_AHB3ENR_FMCEN(v)        BM_RCC_AHB3ENR_FMCEN
#define BF_RCC_AHB3ENR_FMCEN_V(e)       BF_RCC_AHB3ENR_FMCEN(BV_RCC_AHB3ENR_FMCEN__##e)
#define BFM_RCC_AHB3ENR_FMCEN_V(v)      BM_RCC_AHB3ENR_FMCEN
#define BP_RCC_AHB3ENR_FLASHEN          8
#define BM_RCC_AHB3ENR_FLASHEN          0x100
#define BF_RCC_AHB3ENR_FLASHEN(v)       (((v) & 0x1) << 8)
#define BFM_RCC_AHB3ENR_FLASHEN(v)      BM_RCC_AHB3ENR_FLASHEN
#define BF_RCC_AHB3ENR_FLASHEN_V(e)     BF_RCC_AHB3ENR_FLASHEN(BV_RCC_AHB3ENR_FLASHEN__##e)
#define BFM_RCC_AHB3ENR_FLASHEN_V(v)    BM_RCC_AHB3ENR_FLASHEN
#define BP_RCC_AHB3ENR_JPEGDECEN        5
#define BM_RCC_AHB3ENR_JPEGDECEN        0x20
#define BF_RCC_AHB3ENR_JPEGDECEN(v)     (((v) & 0x1) << 5)
#define BFM_RCC_AHB3ENR_JPEGDECEN(v)    BM_RCC_AHB3ENR_JPEGDECEN
#define BF_RCC_AHB3ENR_JPEGDECEN_V(e)   BF_RCC_AHB3ENR_JPEGDECEN(BV_RCC_AHB3ENR_JPEGDECEN__##e)
#define BFM_RCC_AHB3ENR_JPEGDECEN_V(v)  BM_RCC_AHB3ENR_JPEGDECEN
#define BP_RCC_AHB3ENR_DMA2DEN          4
#define BM_RCC_AHB3ENR_DMA2DEN          0x10
#define BF_RCC_AHB3ENR_DMA2DEN(v)       (((v) & 0x1) << 4)
#define BFM_RCC_AHB3ENR_DMA2DEN(v)      BM_RCC_AHB3ENR_DMA2DEN
#define BF_RCC_AHB3ENR_DMA2DEN_V(e)     BF_RCC_AHB3ENR_DMA2DEN(BV_RCC_AHB3ENR_DMA2DEN__##e)
#define BFM_RCC_AHB3ENR_DMA2DEN_V(v)    BM_RCC_AHB3ENR_DMA2DEN
#define BP_RCC_AHB3ENR_MDMAEN           0
#define BM_RCC_AHB3ENR_MDMAEN           0x1
#define BF_RCC_AHB3ENR_MDMAEN(v)        (((v) & 0x1) << 0)
#define BFM_RCC_AHB3ENR_MDMAEN(v)       BM_RCC_AHB3ENR_MDMAEN
#define BF_RCC_AHB3ENR_MDMAEN_V(e)      BF_RCC_AHB3ENR_MDMAEN(BV_RCC_AHB3ENR_MDMAEN__##e)
#define BFM_RCC_AHB3ENR_MDMAEN_V(v)     BM_RCC_AHB3ENR_MDMAEN

#define REG_RCC_AHB3LPENR                   st_reg(RCC_AHB3LPENR)
#define STA_RCC_AHB3LPENR                   (0x58024400 + 0xfc)
#define STO_RCC_AHB3LPENR                   (0xfc)
#define STT_RCC_AHB3LPENR                   STIO_32_RW
#define STN_RCC_AHB3LPENR                   RCC_AHB3LPENR
#define BP_RCC_AHB3LPENR_AXISRAMEN          31
#define BM_RCC_AHB3LPENR_AXISRAMEN          0x80000000
#define BF_RCC_AHB3LPENR_AXISRAMEN(v)       (((v) & 0x1) << 31)
#define BFM_RCC_AHB3LPENR_AXISRAMEN(v)      BM_RCC_AHB3LPENR_AXISRAMEN
#define BF_RCC_AHB3LPENR_AXISRAMEN_V(e)     BF_RCC_AHB3LPENR_AXISRAMEN(BV_RCC_AHB3LPENR_AXISRAMEN__##e)
#define BFM_RCC_AHB3LPENR_AXISRAMEN_V(v)    BM_RCC_AHB3LPENR_AXISRAMEN
#define BP_RCC_AHB3LPENR_ITCMEN             30
#define BM_RCC_AHB3LPENR_ITCMEN             0x40000000
#define BF_RCC_AHB3LPENR_ITCMEN(v)          (((v) & 0x1) << 30)
#define BFM_RCC_AHB3LPENR_ITCMEN(v)         BM_RCC_AHB3LPENR_ITCMEN
#define BF_RCC_AHB3LPENR_ITCMEN_V(e)        BF_RCC_AHB3LPENR_ITCMEN(BV_RCC_AHB3LPENR_ITCMEN__##e)
#define BFM_RCC_AHB3LPENR_ITCMEN_V(v)       BM_RCC_AHB3LPENR_ITCMEN
#define BP_RCC_AHB3LPENR_DTCM2EN            29
#define BM_RCC_AHB3LPENR_DTCM2EN            0x20000000
#define BF_RCC_AHB3LPENR_DTCM2EN(v)         (((v) & 0x1) << 29)
#define BFM_RCC_AHB3LPENR_DTCM2EN(v)        BM_RCC_AHB3LPENR_DTCM2EN
#define BF_RCC_AHB3LPENR_DTCM2EN_V(e)       BF_RCC_AHB3LPENR_DTCM2EN(BV_RCC_AHB3LPENR_DTCM2EN__##e)
#define BFM_RCC_AHB3LPENR_DTCM2EN_V(v)      BM_RCC_AHB3LPENR_DTCM2EN
#define BP_RCC_AHB3LPENR_D1DTCM1EN          28
#define BM_RCC_AHB3LPENR_D1DTCM1EN          0x10000000
#define BF_RCC_AHB3LPENR_D1DTCM1EN(v)       (((v) & 0x1) << 28)
#define BFM_RCC_AHB3LPENR_D1DTCM1EN(v)      BM_RCC_AHB3LPENR_D1DTCM1EN
#define BF_RCC_AHB3LPENR_D1DTCM1EN_V(e)     BF_RCC_AHB3LPENR_D1DTCM1EN(BV_RCC_AHB3LPENR_D1DTCM1EN__##e)
#define BFM_RCC_AHB3LPENR_D1DTCM1EN_V(v)    BM_RCC_AHB3LPENR_D1DTCM1EN
#define BP_RCC_AHB3LPENR_SDMMC1EN           16
#define BM_RCC_AHB3LPENR_SDMMC1EN           0x10000
#define BF_RCC_AHB3LPENR_SDMMC1EN(v)        (((v) & 0x1) << 16)
#define BFM_RCC_AHB3LPENR_SDMMC1EN(v)       BM_RCC_AHB3LPENR_SDMMC1EN
#define BF_RCC_AHB3LPENR_SDMMC1EN_V(e)      BF_RCC_AHB3LPENR_SDMMC1EN(BV_RCC_AHB3LPENR_SDMMC1EN__##e)
#define BFM_RCC_AHB3LPENR_SDMMC1EN_V(v)     BM_RCC_AHB3LPENR_SDMMC1EN
#define BP_RCC_AHB3LPENR_QSPIEN             14
#define BM_RCC_AHB3LPENR_QSPIEN             0x4000
#define BF_RCC_AHB3LPENR_QSPIEN(v)          (((v) & 0x1) << 14)
#define BFM_RCC_AHB3LPENR_QSPIEN(v)         BM_RCC_AHB3LPENR_QSPIEN
#define BF_RCC_AHB3LPENR_QSPIEN_V(e)        BF_RCC_AHB3LPENR_QSPIEN(BV_RCC_AHB3LPENR_QSPIEN__##e)
#define BFM_RCC_AHB3LPENR_QSPIEN_V(v)       BM_RCC_AHB3LPENR_QSPIEN
#define BP_RCC_AHB3LPENR_FMCEN              12
#define BM_RCC_AHB3LPENR_FMCEN              0x1000
#define BF_RCC_AHB3LPENR_FMCEN(v)           (((v) & 0x1) << 12)
#define BFM_RCC_AHB3LPENR_FMCEN(v)          BM_RCC_AHB3LPENR_FMCEN
#define BF_RCC_AHB3LPENR_FMCEN_V(e)         BF_RCC_AHB3LPENR_FMCEN(BV_RCC_AHB3LPENR_FMCEN__##e)
#define BFM_RCC_AHB3LPENR_FMCEN_V(v)        BM_RCC_AHB3LPENR_FMCEN
#define BP_RCC_AHB3LPENR_FLASHEN            8
#define BM_RCC_AHB3LPENR_FLASHEN            0x100
#define BF_RCC_AHB3LPENR_FLASHEN(v)         (((v) & 0x1) << 8)
#define BFM_RCC_AHB3LPENR_FLASHEN(v)        BM_RCC_AHB3LPENR_FLASHEN
#define BF_RCC_AHB3LPENR_FLASHEN_V(e)       BF_RCC_AHB3LPENR_FLASHEN(BV_RCC_AHB3LPENR_FLASHEN__##e)
#define BFM_RCC_AHB3LPENR_FLASHEN_V(v)      BM_RCC_AHB3LPENR_FLASHEN
#define BP_RCC_AHB3LPENR_JPEGDECEN          5
#define BM_RCC_AHB3LPENR_JPEGDECEN          0x20
#define BF_RCC_AHB3LPENR_JPEGDECEN(v)       (((v) & 0x1) << 5)
#define BFM_RCC_AHB3LPENR_JPEGDECEN(v)      BM_RCC_AHB3LPENR_JPEGDECEN
#define BF_RCC_AHB3LPENR_JPEGDECEN_V(e)     BF_RCC_AHB3LPENR_JPEGDECEN(BV_RCC_AHB3LPENR_JPEGDECEN__##e)
#define BFM_RCC_AHB3LPENR_JPEGDECEN_V(v)    BM_RCC_AHB3LPENR_JPEGDECEN
#define BP_RCC_AHB3LPENR_DMA2DEN            4
#define BM_RCC_AHB3LPENR_DMA2DEN            0x10
#define BF_RCC_AHB3LPENR_DMA2DEN(v)         (((v) & 0x1) << 4)
#define BFM_RCC_AHB3LPENR_DMA2DEN(v)        BM_RCC_AHB3LPENR_DMA2DEN
#define BF_RCC_AHB3LPENR_DMA2DEN_V(e)       BF_RCC_AHB3LPENR_DMA2DEN(BV_RCC_AHB3LPENR_DMA2DEN__##e)
#define BFM_RCC_AHB3LPENR_DMA2DEN_V(v)      BM_RCC_AHB3LPENR_DMA2DEN
#define BP_RCC_AHB3LPENR_MDMAEN             0
#define BM_RCC_AHB3LPENR_MDMAEN             0x1
#define BF_RCC_AHB3LPENR_MDMAEN(v)          (((v) & 0x1) << 0)
#define BFM_RCC_AHB3LPENR_MDMAEN(v)         BM_RCC_AHB3LPENR_MDMAEN
#define BF_RCC_AHB3LPENR_MDMAEN_V(e)        BF_RCC_AHB3LPENR_MDMAEN(BV_RCC_AHB3LPENR_MDMAEN__##e)
#define BFM_RCC_AHB3LPENR_MDMAEN_V(v)       BM_RCC_AHB3LPENR_MDMAEN

#define REG_RCC_AHB4ENR                 st_reg(RCC_AHB4ENR)
#define STA_RCC_AHB4ENR                 (0x58024400 + 0xe0)
#define STO_RCC_AHB4ENR                 (0xe0)
#define STT_RCC_AHB4ENR                 STIO_32_RW
#define STN_RCC_AHB4ENR                 RCC_AHB4ENR
#define BP_RCC_AHB4ENR_SRAM4EN          29
#define BM_RCC_AHB4ENR_SRAM4EN          0x20000000
#define BF_RCC_AHB4ENR_SRAM4EN(v)       (((v) & 0x1) << 29)
#define BFM_RCC_AHB4ENR_SRAM4EN(v)      BM_RCC_AHB4ENR_SRAM4EN
#define BF_RCC_AHB4ENR_SRAM4EN_V(e)     BF_RCC_AHB4ENR_SRAM4EN(BV_RCC_AHB4ENR_SRAM4EN__##e)
#define BFM_RCC_AHB4ENR_SRAM4EN_V(v)    BM_RCC_AHB4ENR_SRAM4EN
#define BP_RCC_AHB4ENR_BKPRAMEN         28
#define BM_RCC_AHB4ENR_BKPRAMEN         0x10000000
#define BF_RCC_AHB4ENR_BKPRAMEN(v)      (((v) & 0x1) << 28)
#define BFM_RCC_AHB4ENR_BKPRAMEN(v)     BM_RCC_AHB4ENR_BKPRAMEN
#define BF_RCC_AHB4ENR_BKPRAMEN_V(e)    BF_RCC_AHB4ENR_BKPRAMEN(BV_RCC_AHB4ENR_BKPRAMEN__##e)
#define BFM_RCC_AHB4ENR_BKPRAMEN_V(v)   BM_RCC_AHB4ENR_BKPRAMEN
#define BP_RCC_AHB4ENR_HSEMEN           25
#define BM_RCC_AHB4ENR_HSEMEN           0x2000000
#define BF_RCC_AHB4ENR_HSEMEN(v)        (((v) & 0x1) << 25)
#define BFM_RCC_AHB4ENR_HSEMEN(v)       BM_RCC_AHB4ENR_HSEMEN
#define BF_RCC_AHB4ENR_HSEMEN_V(e)      BF_RCC_AHB4ENR_HSEMEN(BV_RCC_AHB4ENR_HSEMEN__##e)
#define BFM_RCC_AHB4ENR_HSEMEN_V(v)     BM_RCC_AHB4ENR_HSEMEN
#define BP_RCC_AHB4ENR_ADC3EN           24
#define BM_RCC_AHB4ENR_ADC3EN           0x1000000
#define BF_RCC_AHB4ENR_ADC3EN(v)        (((v) & 0x1) << 24)
#define BFM_RCC_AHB4ENR_ADC3EN(v)       BM_RCC_AHB4ENR_ADC3EN
#define BF_RCC_AHB4ENR_ADC3EN_V(e)      BF_RCC_AHB4ENR_ADC3EN(BV_RCC_AHB4ENR_ADC3EN__##e)
#define BFM_RCC_AHB4ENR_ADC3EN_V(v)     BM_RCC_AHB4ENR_ADC3EN
#define BP_RCC_AHB4ENR_BDMAEN           21
#define BM_RCC_AHB4ENR_BDMAEN           0x200000
#define BF_RCC_AHB4ENR_BDMAEN(v)        (((v) & 0x1) << 21)
#define BFM_RCC_AHB4ENR_BDMAEN(v)       BM_RCC_AHB4ENR_BDMAEN
#define BF_RCC_AHB4ENR_BDMAEN_V(e)      BF_RCC_AHB4ENR_BDMAEN(BV_RCC_AHB4ENR_BDMAEN__##e)
#define BFM_RCC_AHB4ENR_BDMAEN_V(v)     BM_RCC_AHB4ENR_BDMAEN
#define BP_RCC_AHB4ENR_CRCEN            19
#define BM_RCC_AHB4ENR_CRCEN            0x80000
#define BF_RCC_AHB4ENR_CRCEN(v)         (((v) & 0x1) << 19)
#define BFM_RCC_AHB4ENR_CRCEN(v)        BM_RCC_AHB4ENR_CRCEN
#define BF_RCC_AHB4ENR_CRCEN_V(e)       BF_RCC_AHB4ENR_CRCEN(BV_RCC_AHB4ENR_CRCEN__##e)
#define BFM_RCC_AHB4ENR_CRCEN_V(v)      BM_RCC_AHB4ENR_CRCEN
#define BP_RCC_AHB4ENR_GPIOKEN          10
#define BM_RCC_AHB4ENR_GPIOKEN          0x400
#define BF_RCC_AHB4ENR_GPIOKEN(v)       (((v) & 0x1) << 10)
#define BFM_RCC_AHB4ENR_GPIOKEN(v)      BM_RCC_AHB4ENR_GPIOKEN
#define BF_RCC_AHB4ENR_GPIOKEN_V(e)     BF_RCC_AHB4ENR_GPIOKEN(BV_RCC_AHB4ENR_GPIOKEN__##e)
#define BFM_RCC_AHB4ENR_GPIOKEN_V(v)    BM_RCC_AHB4ENR_GPIOKEN
#define BP_RCC_AHB4ENR_GPIOJEN          9
#define BM_RCC_AHB4ENR_GPIOJEN          0x200
#define BF_RCC_AHB4ENR_GPIOJEN(v)       (((v) & 0x1) << 9)
#define BFM_RCC_AHB4ENR_GPIOJEN(v)      BM_RCC_AHB4ENR_GPIOJEN
#define BF_RCC_AHB4ENR_GPIOJEN_V(e)     BF_RCC_AHB4ENR_GPIOJEN(BV_RCC_AHB4ENR_GPIOJEN__##e)
#define BFM_RCC_AHB4ENR_GPIOJEN_V(v)    BM_RCC_AHB4ENR_GPIOJEN
#define BP_RCC_AHB4ENR_GPIOIEN          8
#define BM_RCC_AHB4ENR_GPIOIEN          0x100
#define BF_RCC_AHB4ENR_GPIOIEN(v)       (((v) & 0x1) << 8)
#define BFM_RCC_AHB4ENR_GPIOIEN(v)      BM_RCC_AHB4ENR_GPIOIEN
#define BF_RCC_AHB4ENR_GPIOIEN_V(e)     BF_RCC_AHB4ENR_GPIOIEN(BV_RCC_AHB4ENR_GPIOIEN__##e)
#define BFM_RCC_AHB4ENR_GPIOIEN_V(v)    BM_RCC_AHB4ENR_GPIOIEN
#define BP_RCC_AHB4ENR_GPIOHEN          7
#define BM_RCC_AHB4ENR_GPIOHEN          0x80
#define BF_RCC_AHB4ENR_GPIOHEN(v)       (((v) & 0x1) << 7)
#define BFM_RCC_AHB4ENR_GPIOHEN(v)      BM_RCC_AHB4ENR_GPIOHEN
#define BF_RCC_AHB4ENR_GPIOHEN_V(e)     BF_RCC_AHB4ENR_GPIOHEN(BV_RCC_AHB4ENR_GPIOHEN__##e)
#define BFM_RCC_AHB4ENR_GPIOHEN_V(v)    BM_RCC_AHB4ENR_GPIOHEN
#define BP_RCC_AHB4ENR_GPIOGEN          6
#define BM_RCC_AHB4ENR_GPIOGEN          0x40
#define BF_RCC_AHB4ENR_GPIOGEN(v)       (((v) & 0x1) << 6)
#define BFM_RCC_AHB4ENR_GPIOGEN(v)      BM_RCC_AHB4ENR_GPIOGEN
#define BF_RCC_AHB4ENR_GPIOGEN_V(e)     BF_RCC_AHB4ENR_GPIOGEN(BV_RCC_AHB4ENR_GPIOGEN__##e)
#define BFM_RCC_AHB4ENR_GPIOGEN_V(v)    BM_RCC_AHB4ENR_GPIOGEN
#define BP_RCC_AHB4ENR_GPIOFEN          5
#define BM_RCC_AHB4ENR_GPIOFEN          0x20
#define BF_RCC_AHB4ENR_GPIOFEN(v)       (((v) & 0x1) << 5)
#define BFM_RCC_AHB4ENR_GPIOFEN(v)      BM_RCC_AHB4ENR_GPIOFEN
#define BF_RCC_AHB4ENR_GPIOFEN_V(e)     BF_RCC_AHB4ENR_GPIOFEN(BV_RCC_AHB4ENR_GPIOFEN__##e)
#define BFM_RCC_AHB4ENR_GPIOFEN_V(v)    BM_RCC_AHB4ENR_GPIOFEN
#define BP_RCC_AHB4ENR_GPIOEEN          4
#define BM_RCC_AHB4ENR_GPIOEEN          0x10
#define BF_RCC_AHB4ENR_GPIOEEN(v)       (((v) & 0x1) << 4)
#define BFM_RCC_AHB4ENR_GPIOEEN(v)      BM_RCC_AHB4ENR_GPIOEEN
#define BF_RCC_AHB4ENR_GPIOEEN_V(e)     BF_RCC_AHB4ENR_GPIOEEN(BV_RCC_AHB4ENR_GPIOEEN__##e)
#define BFM_RCC_AHB4ENR_GPIOEEN_V(v)    BM_RCC_AHB4ENR_GPIOEEN
#define BP_RCC_AHB4ENR_GPIODEN          3
#define BM_RCC_AHB4ENR_GPIODEN          0x8
#define BF_RCC_AHB4ENR_GPIODEN(v)       (((v) & 0x1) << 3)
#define BFM_RCC_AHB4ENR_GPIODEN(v)      BM_RCC_AHB4ENR_GPIODEN
#define BF_RCC_AHB4ENR_GPIODEN_V(e)     BF_RCC_AHB4ENR_GPIODEN(BV_RCC_AHB4ENR_GPIODEN__##e)
#define BFM_RCC_AHB4ENR_GPIODEN_V(v)    BM_RCC_AHB4ENR_GPIODEN
#define BP_RCC_AHB4ENR_GPIOCEN          2
#define BM_RCC_AHB4ENR_GPIOCEN          0x4
#define BF_RCC_AHB4ENR_GPIOCEN(v)       (((v) & 0x1) << 2)
#define BFM_RCC_AHB4ENR_GPIOCEN(v)      BM_RCC_AHB4ENR_GPIOCEN
#define BF_RCC_AHB4ENR_GPIOCEN_V(e)     BF_RCC_AHB4ENR_GPIOCEN(BV_RCC_AHB4ENR_GPIOCEN__##e)
#define BFM_RCC_AHB4ENR_GPIOCEN_V(v)    BM_RCC_AHB4ENR_GPIOCEN
#define BP_RCC_AHB4ENR_GPIOBEN          1
#define BM_RCC_AHB4ENR_GPIOBEN          0x2
#define BF_RCC_AHB4ENR_GPIOBEN(v)       (((v) & 0x1) << 1)
#define BFM_RCC_AHB4ENR_GPIOBEN(v)      BM_RCC_AHB4ENR_GPIOBEN
#define BF_RCC_AHB4ENR_GPIOBEN_V(e)     BF_RCC_AHB4ENR_GPIOBEN(BV_RCC_AHB4ENR_GPIOBEN__##e)
#define BFM_RCC_AHB4ENR_GPIOBEN_V(v)    BM_RCC_AHB4ENR_GPIOBEN
#define BP_RCC_AHB4ENR_GPIOAEN          0
#define BM_RCC_AHB4ENR_GPIOAEN          0x1
#define BF_RCC_AHB4ENR_GPIOAEN(v)       (((v) & 0x1) << 0)
#define BFM_RCC_AHB4ENR_GPIOAEN(v)      BM_RCC_AHB4ENR_GPIOAEN
#define BF_RCC_AHB4ENR_GPIOAEN_V(e)     BF_RCC_AHB4ENR_GPIOAEN(BV_RCC_AHB4ENR_GPIOAEN__##e)
#define BFM_RCC_AHB4ENR_GPIOAEN_V(v)    BM_RCC_AHB4ENR_GPIOAEN

#define REG_RCC_AHB4LPENR               st_reg(RCC_AHB4LPENR)
#define STA_RCC_AHB4LPENR               (0x58024400 + 0x108)
#define STO_RCC_AHB4LPENR               (0x108)
#define STT_RCC_AHB4LPENR               STIO_32_RW
#define STN_RCC_AHB4LPENR               RCC_AHB4LPENR
#define BP_RCC_AHB4LPENR_SRAM4EN        29
#define BM_RCC_AHB4LPENR_SRAM4EN        0x20000000
#define BF_RCC_AHB4LPENR_SRAM4EN(v)     (((v) & 0x1) << 29)
#define BFM_RCC_AHB4LPENR_SRAM4EN(v)    BM_RCC_AHB4LPENR_SRAM4EN
#define BF_RCC_AHB4LPENR_SRAM4EN_V(e)   BF_RCC_AHB4LPENR_SRAM4EN(BV_RCC_AHB4LPENR_SRAM4EN__##e)
#define BFM_RCC_AHB4LPENR_SRAM4EN_V(v)  BM_RCC_AHB4LPENR_SRAM4EN
#define BP_RCC_AHB4LPENR_BKPRAMEN       28
#define BM_RCC_AHB4LPENR_BKPRAMEN       0x10000000
#define BF_RCC_AHB4LPENR_BKPRAMEN(v)    (((v) & 0x1) << 28)
#define BFM_RCC_AHB4LPENR_BKPRAMEN(v)   BM_RCC_AHB4LPENR_BKPRAMEN
#define BF_RCC_AHB4LPENR_BKPRAMEN_V(e)  BF_RCC_AHB4LPENR_BKPRAMEN(BV_RCC_AHB4LPENR_BKPRAMEN__##e)
#define BFM_RCC_AHB4LPENR_BKPRAMEN_V(v) BM_RCC_AHB4LPENR_BKPRAMEN
#define BP_RCC_AHB4LPENR_HSEMEN         25
#define BM_RCC_AHB4LPENR_HSEMEN         0x2000000
#define BF_RCC_AHB4LPENR_HSEMEN(v)      (((v) & 0x1) << 25)
#define BFM_RCC_AHB4LPENR_HSEMEN(v)     BM_RCC_AHB4LPENR_HSEMEN
#define BF_RCC_AHB4LPENR_HSEMEN_V(e)    BF_RCC_AHB4LPENR_HSEMEN(BV_RCC_AHB4LPENR_HSEMEN__##e)
#define BFM_RCC_AHB4LPENR_HSEMEN_V(v)   BM_RCC_AHB4LPENR_HSEMEN
#define BP_RCC_AHB4LPENR_ADC3EN         24
#define BM_RCC_AHB4LPENR_ADC3EN         0x1000000
#define BF_RCC_AHB4LPENR_ADC3EN(v)      (((v) & 0x1) << 24)
#define BFM_RCC_AHB4LPENR_ADC3EN(v)     BM_RCC_AHB4LPENR_ADC3EN
#define BF_RCC_AHB4LPENR_ADC3EN_V(e)    BF_RCC_AHB4LPENR_ADC3EN(BV_RCC_AHB4LPENR_ADC3EN__##e)
#define BFM_RCC_AHB4LPENR_ADC3EN_V(v)   BM_RCC_AHB4LPENR_ADC3EN
#define BP_RCC_AHB4LPENR_BDMAEN         21
#define BM_RCC_AHB4LPENR_BDMAEN         0x200000
#define BF_RCC_AHB4LPENR_BDMAEN(v)      (((v) & 0x1) << 21)
#define BFM_RCC_AHB4LPENR_BDMAEN(v)     BM_RCC_AHB4LPENR_BDMAEN
#define BF_RCC_AHB4LPENR_BDMAEN_V(e)    BF_RCC_AHB4LPENR_BDMAEN(BV_RCC_AHB4LPENR_BDMAEN__##e)
#define BFM_RCC_AHB4LPENR_BDMAEN_V(v)   BM_RCC_AHB4LPENR_BDMAEN
#define BP_RCC_AHB4LPENR_CRCEN          19
#define BM_RCC_AHB4LPENR_CRCEN          0x80000
#define BF_RCC_AHB4LPENR_CRCEN(v)       (((v) & 0x1) << 19)
#define BFM_RCC_AHB4LPENR_CRCEN(v)      BM_RCC_AHB4LPENR_CRCEN
#define BF_RCC_AHB4LPENR_CRCEN_V(e)     BF_RCC_AHB4LPENR_CRCEN(BV_RCC_AHB4LPENR_CRCEN__##e)
#define BFM_RCC_AHB4LPENR_CRCEN_V(v)    BM_RCC_AHB4LPENR_CRCEN
#define BP_RCC_AHB4LPENR_GPIOKEN        10
#define BM_RCC_AHB4LPENR_GPIOKEN        0x400
#define BF_RCC_AHB4LPENR_GPIOKEN(v)     (((v) & 0x1) << 10)
#define BFM_RCC_AHB4LPENR_GPIOKEN(v)    BM_RCC_AHB4LPENR_GPIOKEN
#define BF_RCC_AHB4LPENR_GPIOKEN_V(e)   BF_RCC_AHB4LPENR_GPIOKEN(BV_RCC_AHB4LPENR_GPIOKEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOKEN_V(v)  BM_RCC_AHB4LPENR_GPIOKEN
#define BP_RCC_AHB4LPENR_GPIOJEN        9
#define BM_RCC_AHB4LPENR_GPIOJEN        0x200
#define BF_RCC_AHB4LPENR_GPIOJEN(v)     (((v) & 0x1) << 9)
#define BFM_RCC_AHB4LPENR_GPIOJEN(v)    BM_RCC_AHB4LPENR_GPIOJEN
#define BF_RCC_AHB4LPENR_GPIOJEN_V(e)   BF_RCC_AHB4LPENR_GPIOJEN(BV_RCC_AHB4LPENR_GPIOJEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOJEN_V(v)  BM_RCC_AHB4LPENR_GPIOJEN
#define BP_RCC_AHB4LPENR_GPIOIEN        8
#define BM_RCC_AHB4LPENR_GPIOIEN        0x100
#define BF_RCC_AHB4LPENR_GPIOIEN(v)     (((v) & 0x1) << 8)
#define BFM_RCC_AHB4LPENR_GPIOIEN(v)    BM_RCC_AHB4LPENR_GPIOIEN
#define BF_RCC_AHB4LPENR_GPIOIEN_V(e)   BF_RCC_AHB4LPENR_GPIOIEN(BV_RCC_AHB4LPENR_GPIOIEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOIEN_V(v)  BM_RCC_AHB4LPENR_GPIOIEN
#define BP_RCC_AHB4LPENR_GPIOHEN        7
#define BM_RCC_AHB4LPENR_GPIOHEN        0x80
#define BF_RCC_AHB4LPENR_GPIOHEN(v)     (((v) & 0x1) << 7)
#define BFM_RCC_AHB4LPENR_GPIOHEN(v)    BM_RCC_AHB4LPENR_GPIOHEN
#define BF_RCC_AHB4LPENR_GPIOHEN_V(e)   BF_RCC_AHB4LPENR_GPIOHEN(BV_RCC_AHB4LPENR_GPIOHEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOHEN_V(v)  BM_RCC_AHB4LPENR_GPIOHEN
#define BP_RCC_AHB4LPENR_GPIOGEN        6
#define BM_RCC_AHB4LPENR_GPIOGEN        0x40
#define BF_RCC_AHB4LPENR_GPIOGEN(v)     (((v) & 0x1) << 6)
#define BFM_RCC_AHB4LPENR_GPIOGEN(v)    BM_RCC_AHB4LPENR_GPIOGEN
#define BF_RCC_AHB4LPENR_GPIOGEN_V(e)   BF_RCC_AHB4LPENR_GPIOGEN(BV_RCC_AHB4LPENR_GPIOGEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOGEN_V(v)  BM_RCC_AHB4LPENR_GPIOGEN
#define BP_RCC_AHB4LPENR_GPIOFEN        5
#define BM_RCC_AHB4LPENR_GPIOFEN        0x20
#define BF_RCC_AHB4LPENR_GPIOFEN(v)     (((v) & 0x1) << 5)
#define BFM_RCC_AHB4LPENR_GPIOFEN(v)    BM_RCC_AHB4LPENR_GPIOFEN
#define BF_RCC_AHB4LPENR_GPIOFEN_V(e)   BF_RCC_AHB4LPENR_GPIOFEN(BV_RCC_AHB4LPENR_GPIOFEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOFEN_V(v)  BM_RCC_AHB4LPENR_GPIOFEN
#define BP_RCC_AHB4LPENR_GPIOEEN        4
#define BM_RCC_AHB4LPENR_GPIOEEN        0x10
#define BF_RCC_AHB4LPENR_GPIOEEN(v)     (((v) & 0x1) << 4)
#define BFM_RCC_AHB4LPENR_GPIOEEN(v)    BM_RCC_AHB4LPENR_GPIOEEN
#define BF_RCC_AHB4LPENR_GPIOEEN_V(e)   BF_RCC_AHB4LPENR_GPIOEEN(BV_RCC_AHB4LPENR_GPIOEEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOEEN_V(v)  BM_RCC_AHB4LPENR_GPIOEEN
#define BP_RCC_AHB4LPENR_GPIODEN        3
#define BM_RCC_AHB4LPENR_GPIODEN        0x8
#define BF_RCC_AHB4LPENR_GPIODEN(v)     (((v) & 0x1) << 3)
#define BFM_RCC_AHB4LPENR_GPIODEN(v)    BM_RCC_AHB4LPENR_GPIODEN
#define BF_RCC_AHB4LPENR_GPIODEN_V(e)   BF_RCC_AHB4LPENR_GPIODEN(BV_RCC_AHB4LPENR_GPIODEN__##e)
#define BFM_RCC_AHB4LPENR_GPIODEN_V(v)  BM_RCC_AHB4LPENR_GPIODEN
#define BP_RCC_AHB4LPENR_GPIOCEN        2
#define BM_RCC_AHB4LPENR_GPIOCEN        0x4
#define BF_RCC_AHB4LPENR_GPIOCEN(v)     (((v) & 0x1) << 2)
#define BFM_RCC_AHB4LPENR_GPIOCEN(v)    BM_RCC_AHB4LPENR_GPIOCEN
#define BF_RCC_AHB4LPENR_GPIOCEN_V(e)   BF_RCC_AHB4LPENR_GPIOCEN(BV_RCC_AHB4LPENR_GPIOCEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOCEN_V(v)  BM_RCC_AHB4LPENR_GPIOCEN
#define BP_RCC_AHB4LPENR_GPIOBEN        1
#define BM_RCC_AHB4LPENR_GPIOBEN        0x2
#define BF_RCC_AHB4LPENR_GPIOBEN(v)     (((v) & 0x1) << 1)
#define BFM_RCC_AHB4LPENR_GPIOBEN(v)    BM_RCC_AHB4LPENR_GPIOBEN
#define BF_RCC_AHB4LPENR_GPIOBEN_V(e)   BF_RCC_AHB4LPENR_GPIOBEN(BV_RCC_AHB4LPENR_GPIOBEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOBEN_V(v)  BM_RCC_AHB4LPENR_GPIOBEN
#define BP_RCC_AHB4LPENR_GPIOAEN        0
#define BM_RCC_AHB4LPENR_GPIOAEN        0x1
#define BF_RCC_AHB4LPENR_GPIOAEN(v)     (((v) & 0x1) << 0)
#define BFM_RCC_AHB4LPENR_GPIOAEN(v)    BM_RCC_AHB4LPENR_GPIOAEN
#define BF_RCC_AHB4LPENR_GPIOAEN_V(e)   BF_RCC_AHB4LPENR_GPIOAEN(BV_RCC_AHB4LPENR_GPIOAEN__##e)
#define BFM_RCC_AHB4LPENR_GPIOAEN_V(v)  BM_RCC_AHB4LPENR_GPIOAEN

#define REG_RCC_APB3ENR                 st_reg(RCC_APB3ENR)
#define STA_RCC_APB3ENR                 (0x58024400 + 0xe4)
#define STO_RCC_APB3ENR                 (0xe4)
#define STT_RCC_APB3ENR                 STIO_32_RW
#define STN_RCC_APB3ENR                 RCC_APB3ENR
#define BP_RCC_APB3ENR_WWDG1EN          6
#define BM_RCC_APB3ENR_WWDG1EN          0x40
#define BF_RCC_APB3ENR_WWDG1EN(v)       (((v) & 0x1) << 6)
#define BFM_RCC_APB3ENR_WWDG1EN(v)      BM_RCC_APB3ENR_WWDG1EN
#define BF_RCC_APB3ENR_WWDG1EN_V(e)     BF_RCC_APB3ENR_WWDG1EN(BV_RCC_APB3ENR_WWDG1EN__##e)
#define BFM_RCC_APB3ENR_WWDG1EN_V(v)    BM_RCC_APB3ENR_WWDG1EN
#define BP_RCC_APB3ENR_LTDCEN           3
#define BM_RCC_APB3ENR_LTDCEN           0x8
#define BF_RCC_APB3ENR_LTDCEN(v)        (((v) & 0x1) << 3)
#define BFM_RCC_APB3ENR_LTDCEN(v)       BM_RCC_APB3ENR_LTDCEN
#define BF_RCC_APB3ENR_LTDCEN_V(e)      BF_RCC_APB3ENR_LTDCEN(BV_RCC_APB3ENR_LTDCEN__##e)
#define BFM_RCC_APB3ENR_LTDCEN_V(v)     BM_RCC_APB3ENR_LTDCEN

#define REG_RCC_APB3LPENR               st_reg(RCC_APB3LPENR)
#define STA_RCC_APB3LPENR               (0x58024400 + 0x10c)
#define STO_RCC_APB3LPENR               (0x10c)
#define STT_RCC_APB3LPENR               STIO_32_RW
#define STN_RCC_APB3LPENR               RCC_APB3LPENR
#define BP_RCC_APB3LPENR_WWDG1EN        6
#define BM_RCC_APB3LPENR_WWDG1EN        0x40
#define BF_RCC_APB3LPENR_WWDG1EN(v)     (((v) & 0x1) << 6)
#define BFM_RCC_APB3LPENR_WWDG1EN(v)    BM_RCC_APB3LPENR_WWDG1EN
#define BF_RCC_APB3LPENR_WWDG1EN_V(e)   BF_RCC_APB3LPENR_WWDG1EN(BV_RCC_APB3LPENR_WWDG1EN__##e)
#define BFM_RCC_APB3LPENR_WWDG1EN_V(v)  BM_RCC_APB3LPENR_WWDG1EN
#define BP_RCC_APB3LPENR_LTDCEN         3
#define BM_RCC_APB3LPENR_LTDCEN         0x8
#define BF_RCC_APB3LPENR_LTDCEN(v)      (((v) & 0x1) << 3)
#define BFM_RCC_APB3LPENR_LTDCEN(v)     BM_RCC_APB3LPENR_LTDCEN
#define BF_RCC_APB3LPENR_LTDCEN_V(e)    BF_RCC_APB3LPENR_LTDCEN(BV_RCC_APB3LPENR_LTDCEN__##e)
#define BFM_RCC_APB3LPENR_LTDCEN_V(v)   BM_RCC_APB3LPENR_LTDCEN

#define REG_RCC_APB1LENR                st_reg(RCC_APB1LENR)
#define STA_RCC_APB1LENR                (0x58024400 + 0xe8)
#define STO_RCC_APB1LENR                (0xe8)
#define STT_RCC_APB1LENR                STIO_32_RW
#define STN_RCC_APB1LENR                RCC_APB1LENR
#define BP_RCC_APB1LENR_UART8EN         31
#define BM_RCC_APB1LENR_UART8EN         0x80000000
#define BF_RCC_APB1LENR_UART8EN(v)      (((v) & 0x1) << 31)
#define BFM_RCC_APB1LENR_UART8EN(v)     BM_RCC_APB1LENR_UART8EN
#define BF_RCC_APB1LENR_UART8EN_V(e)    BF_RCC_APB1LENR_UART8EN(BV_RCC_APB1LENR_UART8EN__##e)
#define BFM_RCC_APB1LENR_UART8EN_V(v)   BM_RCC_APB1LENR_UART8EN
#define BP_RCC_APB1LENR_UART7EN         30
#define BM_RCC_APB1LENR_UART7EN         0x40000000
#define BF_RCC_APB1LENR_UART7EN(v)      (((v) & 0x1) << 30)
#define BFM_RCC_APB1LENR_UART7EN(v)     BM_RCC_APB1LENR_UART7EN
#define BF_RCC_APB1LENR_UART7EN_V(e)    BF_RCC_APB1LENR_UART7EN(BV_RCC_APB1LENR_UART7EN__##e)
#define BFM_RCC_APB1LENR_UART7EN_V(v)   BM_RCC_APB1LENR_UART7EN
#define BP_RCC_APB1LENR_DAC12EN         29
#define BM_RCC_APB1LENR_DAC12EN         0x20000000
#define BF_RCC_APB1LENR_DAC12EN(v)      (((v) & 0x1) << 29)
#define BFM_RCC_APB1LENR_DAC12EN(v)     BM_RCC_APB1LENR_DAC12EN
#define BF_RCC_APB1LENR_DAC12EN_V(e)    BF_RCC_APB1LENR_DAC12EN(BV_RCC_APB1LENR_DAC12EN__##e)
#define BFM_RCC_APB1LENR_DAC12EN_V(v)   BM_RCC_APB1LENR_DAC12EN
#define BP_RCC_APB1LENR_CECEN           27
#define BM_RCC_APB1LENR_CECEN           0x8000000
#define BF_RCC_APB1LENR_CECEN(v)        (((v) & 0x1) << 27)
#define BFM_RCC_APB1LENR_CECEN(v)       BM_RCC_APB1LENR_CECEN
#define BF_RCC_APB1LENR_CECEN_V(e)      BF_RCC_APB1LENR_CECEN(BV_RCC_APB1LENR_CECEN__##e)
#define BFM_RCC_APB1LENR_CECEN_V(v)     BM_RCC_APB1LENR_CECEN
#define BP_RCC_APB1LENR_I2C3EN          23
#define BM_RCC_APB1LENR_I2C3EN          0x800000
#define BF_RCC_APB1LENR_I2C3EN(v)       (((v) & 0x1) << 23)
#define BFM_RCC_APB1LENR_I2C3EN(v)      BM_RCC_APB1LENR_I2C3EN
#define BF_RCC_APB1LENR_I2C3EN_V(e)     BF_RCC_APB1LENR_I2C3EN(BV_RCC_APB1LENR_I2C3EN__##e)
#define BFM_RCC_APB1LENR_I2C3EN_V(v)    BM_RCC_APB1LENR_I2C3EN
#define BP_RCC_APB1LENR_I2C2EN          22
#define BM_RCC_APB1LENR_I2C2EN          0x400000
#define BF_RCC_APB1LENR_I2C2EN(v)       (((v) & 0x1) << 22)
#define BFM_RCC_APB1LENR_I2C2EN(v)      BM_RCC_APB1LENR_I2C2EN
#define BF_RCC_APB1LENR_I2C2EN_V(e)     BF_RCC_APB1LENR_I2C2EN(BV_RCC_APB1LENR_I2C2EN__##e)
#define BFM_RCC_APB1LENR_I2C2EN_V(v)    BM_RCC_APB1LENR_I2C2EN
#define BP_RCC_APB1LENR_I2C1EN          21
#define BM_RCC_APB1LENR_I2C1EN          0x200000
#define BF_RCC_APB1LENR_I2C1EN(v)       (((v) & 0x1) << 21)
#define BFM_RCC_APB1LENR_I2C1EN(v)      BM_RCC_APB1LENR_I2C1EN
#define BF_RCC_APB1LENR_I2C1EN_V(e)     BF_RCC_APB1LENR_I2C1EN(BV_RCC_APB1LENR_I2C1EN__##e)
#define BFM_RCC_APB1LENR_I2C1EN_V(v)    BM_RCC_APB1LENR_I2C1EN
#define BP_RCC_APB1LENR_UART5EN         20
#define BM_RCC_APB1LENR_UART5EN         0x100000
#define BF_RCC_APB1LENR_UART5EN(v)      (((v) & 0x1) << 20)
#define BFM_RCC_APB1LENR_UART5EN(v)     BM_RCC_APB1LENR_UART5EN
#define BF_RCC_APB1LENR_UART5EN_V(e)    BF_RCC_APB1LENR_UART5EN(BV_RCC_APB1LENR_UART5EN__##e)
#define BFM_RCC_APB1LENR_UART5EN_V(v)   BM_RCC_APB1LENR_UART5EN
#define BP_RCC_APB1LENR_UART4EN         19
#define BM_RCC_APB1LENR_UART4EN         0x80000
#define BF_RCC_APB1LENR_UART4EN(v)      (((v) & 0x1) << 19)
#define BFM_RCC_APB1LENR_UART4EN(v)     BM_RCC_APB1LENR_UART4EN
#define BF_RCC_APB1LENR_UART4EN_V(e)    BF_RCC_APB1LENR_UART4EN(BV_RCC_APB1LENR_UART4EN__##e)
#define BFM_RCC_APB1LENR_UART4EN_V(v)   BM_RCC_APB1LENR_UART4EN
#define BP_RCC_APB1LENR_USART3EN        18
#define BM_RCC_APB1LENR_USART3EN        0x40000
#define BF_RCC_APB1LENR_USART3EN(v)     (((v) & 0x1) << 18)
#define BFM_RCC_APB1LENR_USART3EN(v)    BM_RCC_APB1LENR_USART3EN
#define BF_RCC_APB1LENR_USART3EN_V(e)   BF_RCC_APB1LENR_USART3EN(BV_RCC_APB1LENR_USART3EN__##e)
#define BFM_RCC_APB1LENR_USART3EN_V(v)  BM_RCC_APB1LENR_USART3EN
#define BP_RCC_APB1LENR_USART2EN        17
#define BM_RCC_APB1LENR_USART2EN        0x20000
#define BF_RCC_APB1LENR_USART2EN(v)     (((v) & 0x1) << 17)
#define BFM_RCC_APB1LENR_USART2EN(v)    BM_RCC_APB1LENR_USART2EN
#define BF_RCC_APB1LENR_USART2EN_V(e)   BF_RCC_APB1LENR_USART2EN(BV_RCC_APB1LENR_USART2EN__##e)
#define BFM_RCC_APB1LENR_USART2EN_V(v)  BM_RCC_APB1LENR_USART2EN
#define BP_RCC_APB1LENR_SPDIFRXEN       16
#define BM_RCC_APB1LENR_SPDIFRXEN       0x10000
#define BF_RCC_APB1LENR_SPDIFRXEN(v)    (((v) & 0x1) << 16)
#define BFM_RCC_APB1LENR_SPDIFRXEN(v)   BM_RCC_APB1LENR_SPDIFRXEN
#define BF_RCC_APB1LENR_SPDIFRXEN_V(e)  BF_RCC_APB1LENR_SPDIFRXEN(BV_RCC_APB1LENR_SPDIFRXEN__##e)
#define BFM_RCC_APB1LENR_SPDIFRXEN_V(v) BM_RCC_APB1LENR_SPDIFRXEN
#define BP_RCC_APB1LENR_SPI3EN          15
#define BM_RCC_APB1LENR_SPI3EN          0x8000
#define BF_RCC_APB1LENR_SPI3EN(v)       (((v) & 0x1) << 15)
#define BFM_RCC_APB1LENR_SPI3EN(v)      BM_RCC_APB1LENR_SPI3EN
#define BF_RCC_APB1LENR_SPI3EN_V(e)     BF_RCC_APB1LENR_SPI3EN(BV_RCC_APB1LENR_SPI3EN__##e)
#define BFM_RCC_APB1LENR_SPI3EN_V(v)    BM_RCC_APB1LENR_SPI3EN
#define BP_RCC_APB1LENR_SPI2EN          14
#define BM_RCC_APB1LENR_SPI2EN          0x4000
#define BF_RCC_APB1LENR_SPI2EN(v)       (((v) & 0x1) << 14)
#define BFM_RCC_APB1LENR_SPI2EN(v)      BM_RCC_APB1LENR_SPI2EN
#define BF_RCC_APB1LENR_SPI2EN_V(e)     BF_RCC_APB1LENR_SPI2EN(BV_RCC_APB1LENR_SPI2EN__##e)
#define BFM_RCC_APB1LENR_SPI2EN_V(v)    BM_RCC_APB1LENR_SPI2EN
#define BP_RCC_APB1LENR_LPTIM1EN        9
#define BM_RCC_APB1LENR_LPTIM1EN        0x200
#define BF_RCC_APB1LENR_LPTIM1EN(v)     (((v) & 0x1) << 9)
#define BFM_RCC_APB1LENR_LPTIM1EN(v)    BM_RCC_APB1LENR_LPTIM1EN
#define BF_RCC_APB1LENR_LPTIM1EN_V(e)   BF_RCC_APB1LENR_LPTIM1EN(BV_RCC_APB1LENR_LPTIM1EN__##e)
#define BFM_RCC_APB1LENR_LPTIM1EN_V(v)  BM_RCC_APB1LENR_LPTIM1EN
#define BP_RCC_APB1LENR_TIM14EN         8
#define BM_RCC_APB1LENR_TIM14EN         0x100
#define BF_RCC_APB1LENR_TIM14EN(v)      (((v) & 0x1) << 8)
#define BFM_RCC_APB1LENR_TIM14EN(v)     BM_RCC_APB1LENR_TIM14EN
#define BF_RCC_APB1LENR_TIM14EN_V(e)    BF_RCC_APB1LENR_TIM14EN(BV_RCC_APB1LENR_TIM14EN__##e)
#define BFM_RCC_APB1LENR_TIM14EN_V(v)   BM_RCC_APB1LENR_TIM14EN
#define BP_RCC_APB1LENR_TIM13EN         7
#define BM_RCC_APB1LENR_TIM13EN         0x80
#define BF_RCC_APB1LENR_TIM13EN(v)      (((v) & 0x1) << 7)
#define BFM_RCC_APB1LENR_TIM13EN(v)     BM_RCC_APB1LENR_TIM13EN
#define BF_RCC_APB1LENR_TIM13EN_V(e)    BF_RCC_APB1LENR_TIM13EN(BV_RCC_APB1LENR_TIM13EN__##e)
#define BFM_RCC_APB1LENR_TIM13EN_V(v)   BM_RCC_APB1LENR_TIM13EN
#define BP_RCC_APB1LENR_TIM12EN         6
#define BM_RCC_APB1LENR_TIM12EN         0x40
#define BF_RCC_APB1LENR_TIM12EN(v)      (((v) & 0x1) << 6)
#define BFM_RCC_APB1LENR_TIM12EN(v)     BM_RCC_APB1LENR_TIM12EN
#define BF_RCC_APB1LENR_TIM12EN_V(e)    BF_RCC_APB1LENR_TIM12EN(BV_RCC_APB1LENR_TIM12EN__##e)
#define BFM_RCC_APB1LENR_TIM12EN_V(v)   BM_RCC_APB1LENR_TIM12EN
#define BP_RCC_APB1LENR_TIM7EN          5
#define BM_RCC_APB1LENR_TIM7EN          0x20
#define BF_RCC_APB1LENR_TIM7EN(v)       (((v) & 0x1) << 5)
#define BFM_RCC_APB1LENR_TIM7EN(v)      BM_RCC_APB1LENR_TIM7EN
#define BF_RCC_APB1LENR_TIM7EN_V(e)     BF_RCC_APB1LENR_TIM7EN(BV_RCC_APB1LENR_TIM7EN__##e)
#define BFM_RCC_APB1LENR_TIM7EN_V(v)    BM_RCC_APB1LENR_TIM7EN
#define BP_RCC_APB1LENR_TIM6EN          4
#define BM_RCC_APB1LENR_TIM6EN          0x10
#define BF_RCC_APB1LENR_TIM6EN(v)       (((v) & 0x1) << 4)
#define BFM_RCC_APB1LENR_TIM6EN(v)      BM_RCC_APB1LENR_TIM6EN
#define BF_RCC_APB1LENR_TIM6EN_V(e)     BF_RCC_APB1LENR_TIM6EN(BV_RCC_APB1LENR_TIM6EN__##e)
#define BFM_RCC_APB1LENR_TIM6EN_V(v)    BM_RCC_APB1LENR_TIM6EN
#define BP_RCC_APB1LENR_TIM5EN          3
#define BM_RCC_APB1LENR_TIM5EN          0x8
#define BF_RCC_APB1LENR_TIM5EN(v)       (((v) & 0x1) << 3)
#define BFM_RCC_APB1LENR_TIM5EN(v)      BM_RCC_APB1LENR_TIM5EN
#define BF_RCC_APB1LENR_TIM5EN_V(e)     BF_RCC_APB1LENR_TIM5EN(BV_RCC_APB1LENR_TIM5EN__##e)
#define BFM_RCC_APB1LENR_TIM5EN_V(v)    BM_RCC_APB1LENR_TIM5EN
#define BP_RCC_APB1LENR_TIM4EN          2
#define BM_RCC_APB1LENR_TIM4EN          0x4
#define BF_RCC_APB1LENR_TIM4EN(v)       (((v) & 0x1) << 2)
#define BFM_RCC_APB1LENR_TIM4EN(v)      BM_RCC_APB1LENR_TIM4EN
#define BF_RCC_APB1LENR_TIM4EN_V(e)     BF_RCC_APB1LENR_TIM4EN(BV_RCC_APB1LENR_TIM4EN__##e)
#define BFM_RCC_APB1LENR_TIM4EN_V(v)    BM_RCC_APB1LENR_TIM4EN
#define BP_RCC_APB1LENR_TIM3EN          1
#define BM_RCC_APB1LENR_TIM3EN          0x2
#define BF_RCC_APB1LENR_TIM3EN(v)       (((v) & 0x1) << 1)
#define BFM_RCC_APB1LENR_TIM3EN(v)      BM_RCC_APB1LENR_TIM3EN
#define BF_RCC_APB1LENR_TIM3EN_V(e)     BF_RCC_APB1LENR_TIM3EN(BV_RCC_APB1LENR_TIM3EN__##e)
#define BFM_RCC_APB1LENR_TIM3EN_V(v)    BM_RCC_APB1LENR_TIM3EN
#define BP_RCC_APB1LENR_TIM2EN          0
#define BM_RCC_APB1LENR_TIM2EN          0x1
#define BF_RCC_APB1LENR_TIM2EN(v)       (((v) & 0x1) << 0)
#define BFM_RCC_APB1LENR_TIM2EN(v)      BM_RCC_APB1LENR_TIM2EN
#define BF_RCC_APB1LENR_TIM2EN_V(e)     BF_RCC_APB1LENR_TIM2EN(BV_RCC_APB1LENR_TIM2EN__##e)
#define BFM_RCC_APB1LENR_TIM2EN_V(v)    BM_RCC_APB1LENR_TIM2EN

#define REG_RCC_APB1LLPENR                  st_reg(RCC_APB1LLPENR)
#define STA_RCC_APB1LLPENR                  (0x58024400 + 0x110)
#define STO_RCC_APB1LLPENR                  (0x110)
#define STT_RCC_APB1LLPENR                  STIO_32_RW
#define STN_RCC_APB1LLPENR                  RCC_APB1LLPENR
#define BP_RCC_APB1LLPENR_UART8EN           31
#define BM_RCC_APB1LLPENR_UART8EN           0x80000000
#define BF_RCC_APB1LLPENR_UART8EN(v)        (((v) & 0x1) << 31)
#define BFM_RCC_APB1LLPENR_UART8EN(v)       BM_RCC_APB1LLPENR_UART8EN
#define BF_RCC_APB1LLPENR_UART8EN_V(e)      BF_RCC_APB1LLPENR_UART8EN(BV_RCC_APB1LLPENR_UART8EN__##e)
#define BFM_RCC_APB1LLPENR_UART8EN_V(v)     BM_RCC_APB1LLPENR_UART8EN
#define BP_RCC_APB1LLPENR_UART7EN           30
#define BM_RCC_APB1LLPENR_UART7EN           0x40000000
#define BF_RCC_APB1LLPENR_UART7EN(v)        (((v) & 0x1) << 30)
#define BFM_RCC_APB1LLPENR_UART7EN(v)       BM_RCC_APB1LLPENR_UART7EN
#define BF_RCC_APB1LLPENR_UART7EN_V(e)      BF_RCC_APB1LLPENR_UART7EN(BV_RCC_APB1LLPENR_UART7EN__##e)
#define BFM_RCC_APB1LLPENR_UART7EN_V(v)     BM_RCC_APB1LLPENR_UART7EN
#define BP_RCC_APB1LLPENR_DAC12EN           29
#define BM_RCC_APB1LLPENR_DAC12EN           0x20000000
#define BF_RCC_APB1LLPENR_DAC12EN(v)        (((v) & 0x1) << 29)
#define BFM_RCC_APB1LLPENR_DAC12EN(v)       BM_RCC_APB1LLPENR_DAC12EN
#define BF_RCC_APB1LLPENR_DAC12EN_V(e)      BF_RCC_APB1LLPENR_DAC12EN(BV_RCC_APB1LLPENR_DAC12EN__##e)
#define BFM_RCC_APB1LLPENR_DAC12EN_V(v)     BM_RCC_APB1LLPENR_DAC12EN
#define BP_RCC_APB1LLPENR_CECEN             27
#define BM_RCC_APB1LLPENR_CECEN             0x8000000
#define BF_RCC_APB1LLPENR_CECEN(v)          (((v) & 0x1) << 27)
#define BFM_RCC_APB1LLPENR_CECEN(v)         BM_RCC_APB1LLPENR_CECEN
#define BF_RCC_APB1LLPENR_CECEN_V(e)        BF_RCC_APB1LLPENR_CECEN(BV_RCC_APB1LLPENR_CECEN__##e)
#define BFM_RCC_APB1LLPENR_CECEN_V(v)       BM_RCC_APB1LLPENR_CECEN
#define BP_RCC_APB1LLPENR_I2C3EN            23
#define BM_RCC_APB1LLPENR_I2C3EN            0x800000
#define BF_RCC_APB1LLPENR_I2C3EN(v)         (((v) & 0x1) << 23)
#define BFM_RCC_APB1LLPENR_I2C3EN(v)        BM_RCC_APB1LLPENR_I2C3EN
#define BF_RCC_APB1LLPENR_I2C3EN_V(e)       BF_RCC_APB1LLPENR_I2C3EN(BV_RCC_APB1LLPENR_I2C3EN__##e)
#define BFM_RCC_APB1LLPENR_I2C3EN_V(v)      BM_RCC_APB1LLPENR_I2C3EN
#define BP_RCC_APB1LLPENR_I2C2EN            22
#define BM_RCC_APB1LLPENR_I2C2EN            0x400000
#define BF_RCC_APB1LLPENR_I2C2EN(v)         (((v) & 0x1) << 22)
#define BFM_RCC_APB1LLPENR_I2C2EN(v)        BM_RCC_APB1LLPENR_I2C2EN
#define BF_RCC_APB1LLPENR_I2C2EN_V(e)       BF_RCC_APB1LLPENR_I2C2EN(BV_RCC_APB1LLPENR_I2C2EN__##e)
#define BFM_RCC_APB1LLPENR_I2C2EN_V(v)      BM_RCC_APB1LLPENR_I2C2EN
#define BP_RCC_APB1LLPENR_I2C1EN            21
#define BM_RCC_APB1LLPENR_I2C1EN            0x200000
#define BF_RCC_APB1LLPENR_I2C1EN(v)         (((v) & 0x1) << 21)
#define BFM_RCC_APB1LLPENR_I2C1EN(v)        BM_RCC_APB1LLPENR_I2C1EN
#define BF_RCC_APB1LLPENR_I2C1EN_V(e)       BF_RCC_APB1LLPENR_I2C1EN(BV_RCC_APB1LLPENR_I2C1EN__##e)
#define BFM_RCC_APB1LLPENR_I2C1EN_V(v)      BM_RCC_APB1LLPENR_I2C1EN
#define BP_RCC_APB1LLPENR_UART5EN           20
#define BM_RCC_APB1LLPENR_UART5EN           0x100000
#define BF_RCC_APB1LLPENR_UART5EN(v)        (((v) & 0x1) << 20)
#define BFM_RCC_APB1LLPENR_UART5EN(v)       BM_RCC_APB1LLPENR_UART5EN
#define BF_RCC_APB1LLPENR_UART5EN_V(e)      BF_RCC_APB1LLPENR_UART5EN(BV_RCC_APB1LLPENR_UART5EN__##e)
#define BFM_RCC_APB1LLPENR_UART5EN_V(v)     BM_RCC_APB1LLPENR_UART5EN
#define BP_RCC_APB1LLPENR_UART4EN           19
#define BM_RCC_APB1LLPENR_UART4EN           0x80000
#define BF_RCC_APB1LLPENR_UART4EN(v)        (((v) & 0x1) << 19)
#define BFM_RCC_APB1LLPENR_UART4EN(v)       BM_RCC_APB1LLPENR_UART4EN
#define BF_RCC_APB1LLPENR_UART4EN_V(e)      BF_RCC_APB1LLPENR_UART4EN(BV_RCC_APB1LLPENR_UART4EN__##e)
#define BFM_RCC_APB1LLPENR_UART4EN_V(v)     BM_RCC_APB1LLPENR_UART4EN
#define BP_RCC_APB1LLPENR_USART3EN          18
#define BM_RCC_APB1LLPENR_USART3EN          0x40000
#define BF_RCC_APB1LLPENR_USART3EN(v)       (((v) & 0x1) << 18)
#define BFM_RCC_APB1LLPENR_USART3EN(v)      BM_RCC_APB1LLPENR_USART3EN
#define BF_RCC_APB1LLPENR_USART3EN_V(e)     BF_RCC_APB1LLPENR_USART3EN(BV_RCC_APB1LLPENR_USART3EN__##e)
#define BFM_RCC_APB1LLPENR_USART3EN_V(v)    BM_RCC_APB1LLPENR_USART3EN
#define BP_RCC_APB1LLPENR_USART2EN          17
#define BM_RCC_APB1LLPENR_USART2EN          0x20000
#define BF_RCC_APB1LLPENR_USART2EN(v)       (((v) & 0x1) << 17)
#define BFM_RCC_APB1LLPENR_USART2EN(v)      BM_RCC_APB1LLPENR_USART2EN
#define BF_RCC_APB1LLPENR_USART2EN_V(e)     BF_RCC_APB1LLPENR_USART2EN(BV_RCC_APB1LLPENR_USART2EN__##e)
#define BFM_RCC_APB1LLPENR_USART2EN_V(v)    BM_RCC_APB1LLPENR_USART2EN
#define BP_RCC_APB1LLPENR_SPDIFRXEN         16
#define BM_RCC_APB1LLPENR_SPDIFRXEN         0x10000
#define BF_RCC_APB1LLPENR_SPDIFRXEN(v)      (((v) & 0x1) << 16)
#define BFM_RCC_APB1LLPENR_SPDIFRXEN(v)     BM_RCC_APB1LLPENR_SPDIFRXEN
#define BF_RCC_APB1LLPENR_SPDIFRXEN_V(e)    BF_RCC_APB1LLPENR_SPDIFRXEN(BV_RCC_APB1LLPENR_SPDIFRXEN__##e)
#define BFM_RCC_APB1LLPENR_SPDIFRXEN_V(v)   BM_RCC_APB1LLPENR_SPDIFRXEN
#define BP_RCC_APB1LLPENR_SPI3EN            15
#define BM_RCC_APB1LLPENR_SPI3EN            0x8000
#define BF_RCC_APB1LLPENR_SPI3EN(v)         (((v) & 0x1) << 15)
#define BFM_RCC_APB1LLPENR_SPI3EN(v)        BM_RCC_APB1LLPENR_SPI3EN
#define BF_RCC_APB1LLPENR_SPI3EN_V(e)       BF_RCC_APB1LLPENR_SPI3EN(BV_RCC_APB1LLPENR_SPI3EN__##e)
#define BFM_RCC_APB1LLPENR_SPI3EN_V(v)      BM_RCC_APB1LLPENR_SPI3EN
#define BP_RCC_APB1LLPENR_SPI2EN            14
#define BM_RCC_APB1LLPENR_SPI2EN            0x4000
#define BF_RCC_APB1LLPENR_SPI2EN(v)         (((v) & 0x1) << 14)
#define BFM_RCC_APB1LLPENR_SPI2EN(v)        BM_RCC_APB1LLPENR_SPI2EN
#define BF_RCC_APB1LLPENR_SPI2EN_V(e)       BF_RCC_APB1LLPENR_SPI2EN(BV_RCC_APB1LLPENR_SPI2EN__##e)
#define BFM_RCC_APB1LLPENR_SPI2EN_V(v)      BM_RCC_APB1LLPENR_SPI2EN
#define BP_RCC_APB1LLPENR_LPTIM1EN          9
#define BM_RCC_APB1LLPENR_LPTIM1EN          0x200
#define BF_RCC_APB1LLPENR_LPTIM1EN(v)       (((v) & 0x1) << 9)
#define BFM_RCC_APB1LLPENR_LPTIM1EN(v)      BM_RCC_APB1LLPENR_LPTIM1EN
#define BF_RCC_APB1LLPENR_LPTIM1EN_V(e)     BF_RCC_APB1LLPENR_LPTIM1EN(BV_RCC_APB1LLPENR_LPTIM1EN__##e)
#define BFM_RCC_APB1LLPENR_LPTIM1EN_V(v)    BM_RCC_APB1LLPENR_LPTIM1EN
#define BP_RCC_APB1LLPENR_TIM14EN           8
#define BM_RCC_APB1LLPENR_TIM14EN           0x100
#define BF_RCC_APB1LLPENR_TIM14EN(v)        (((v) & 0x1) << 8)
#define BFM_RCC_APB1LLPENR_TIM14EN(v)       BM_RCC_APB1LLPENR_TIM14EN
#define BF_RCC_APB1LLPENR_TIM14EN_V(e)      BF_RCC_APB1LLPENR_TIM14EN(BV_RCC_APB1LLPENR_TIM14EN__##e)
#define BFM_RCC_APB1LLPENR_TIM14EN_V(v)     BM_RCC_APB1LLPENR_TIM14EN
#define BP_RCC_APB1LLPENR_TIM13EN           7
#define BM_RCC_APB1LLPENR_TIM13EN           0x80
#define BF_RCC_APB1LLPENR_TIM13EN(v)        (((v) & 0x1) << 7)
#define BFM_RCC_APB1LLPENR_TIM13EN(v)       BM_RCC_APB1LLPENR_TIM13EN
#define BF_RCC_APB1LLPENR_TIM13EN_V(e)      BF_RCC_APB1LLPENR_TIM13EN(BV_RCC_APB1LLPENR_TIM13EN__##e)
#define BFM_RCC_APB1LLPENR_TIM13EN_V(v)     BM_RCC_APB1LLPENR_TIM13EN
#define BP_RCC_APB1LLPENR_TIM12EN           6
#define BM_RCC_APB1LLPENR_TIM12EN           0x40
#define BF_RCC_APB1LLPENR_TIM12EN(v)        (((v) & 0x1) << 6)
#define BFM_RCC_APB1LLPENR_TIM12EN(v)       BM_RCC_APB1LLPENR_TIM12EN
#define BF_RCC_APB1LLPENR_TIM12EN_V(e)      BF_RCC_APB1LLPENR_TIM12EN(BV_RCC_APB1LLPENR_TIM12EN__##e)
#define BFM_RCC_APB1LLPENR_TIM12EN_V(v)     BM_RCC_APB1LLPENR_TIM12EN
#define BP_RCC_APB1LLPENR_TIM7EN            5
#define BM_RCC_APB1LLPENR_TIM7EN            0x20
#define BF_RCC_APB1LLPENR_TIM7EN(v)         (((v) & 0x1) << 5)
#define BFM_RCC_APB1LLPENR_TIM7EN(v)        BM_RCC_APB1LLPENR_TIM7EN
#define BF_RCC_APB1LLPENR_TIM7EN_V(e)       BF_RCC_APB1LLPENR_TIM7EN(BV_RCC_APB1LLPENR_TIM7EN__##e)
#define BFM_RCC_APB1LLPENR_TIM7EN_V(v)      BM_RCC_APB1LLPENR_TIM7EN
#define BP_RCC_APB1LLPENR_TIM6EN            4
#define BM_RCC_APB1LLPENR_TIM6EN            0x10
#define BF_RCC_APB1LLPENR_TIM6EN(v)         (((v) & 0x1) << 4)
#define BFM_RCC_APB1LLPENR_TIM6EN(v)        BM_RCC_APB1LLPENR_TIM6EN
#define BF_RCC_APB1LLPENR_TIM6EN_V(e)       BF_RCC_APB1LLPENR_TIM6EN(BV_RCC_APB1LLPENR_TIM6EN__##e)
#define BFM_RCC_APB1LLPENR_TIM6EN_V(v)      BM_RCC_APB1LLPENR_TIM6EN
#define BP_RCC_APB1LLPENR_TIM5EN            3
#define BM_RCC_APB1LLPENR_TIM5EN            0x8
#define BF_RCC_APB1LLPENR_TIM5EN(v)         (((v) & 0x1) << 3)
#define BFM_RCC_APB1LLPENR_TIM5EN(v)        BM_RCC_APB1LLPENR_TIM5EN
#define BF_RCC_APB1LLPENR_TIM5EN_V(e)       BF_RCC_APB1LLPENR_TIM5EN(BV_RCC_APB1LLPENR_TIM5EN__##e)
#define BFM_RCC_APB1LLPENR_TIM5EN_V(v)      BM_RCC_APB1LLPENR_TIM5EN
#define BP_RCC_APB1LLPENR_TIM4EN            2
#define BM_RCC_APB1LLPENR_TIM4EN            0x4
#define BF_RCC_APB1LLPENR_TIM4EN(v)         (((v) & 0x1) << 2)
#define BFM_RCC_APB1LLPENR_TIM4EN(v)        BM_RCC_APB1LLPENR_TIM4EN
#define BF_RCC_APB1LLPENR_TIM4EN_V(e)       BF_RCC_APB1LLPENR_TIM4EN(BV_RCC_APB1LLPENR_TIM4EN__##e)
#define BFM_RCC_APB1LLPENR_TIM4EN_V(v)      BM_RCC_APB1LLPENR_TIM4EN
#define BP_RCC_APB1LLPENR_TIM3EN            1
#define BM_RCC_APB1LLPENR_TIM3EN            0x2
#define BF_RCC_APB1LLPENR_TIM3EN(v)         (((v) & 0x1) << 1)
#define BFM_RCC_APB1LLPENR_TIM3EN(v)        BM_RCC_APB1LLPENR_TIM3EN
#define BF_RCC_APB1LLPENR_TIM3EN_V(e)       BF_RCC_APB1LLPENR_TIM3EN(BV_RCC_APB1LLPENR_TIM3EN__##e)
#define BFM_RCC_APB1LLPENR_TIM3EN_V(v)      BM_RCC_APB1LLPENR_TIM3EN
#define BP_RCC_APB1LLPENR_TIM2EN            0
#define BM_RCC_APB1LLPENR_TIM2EN            0x1
#define BF_RCC_APB1LLPENR_TIM2EN(v)         (((v) & 0x1) << 0)
#define BFM_RCC_APB1LLPENR_TIM2EN(v)        BM_RCC_APB1LLPENR_TIM2EN
#define BF_RCC_APB1LLPENR_TIM2EN_V(e)       BF_RCC_APB1LLPENR_TIM2EN(BV_RCC_APB1LLPENR_TIM2EN__##e)
#define BFM_RCC_APB1LLPENR_TIM2EN_V(v)      BM_RCC_APB1LLPENR_TIM2EN

#define REG_RCC_APB1HENR                st_reg(RCC_APB1HENR)
#define STA_RCC_APB1HENR                (0x58024400 + 0xec)
#define STO_RCC_APB1HENR                (0xec)
#define STT_RCC_APB1HENR                STIO_32_RW
#define STN_RCC_APB1HENR                RCC_APB1HENR
#define BP_RCC_APB1HENR_FDCANEN         8
#define BM_RCC_APB1HENR_FDCANEN         0x100
#define BF_RCC_APB1HENR_FDCANEN(v)      (((v) & 0x1) << 8)
#define BFM_RCC_APB1HENR_FDCANEN(v)     BM_RCC_APB1HENR_FDCANEN
#define BF_RCC_APB1HENR_FDCANEN_V(e)    BF_RCC_APB1HENR_FDCANEN(BV_RCC_APB1HENR_FDCANEN__##e)
#define BFM_RCC_APB1HENR_FDCANEN_V(v)   BM_RCC_APB1HENR_FDCANEN
#define BP_RCC_APB1HENR_MDIOSEN         5
#define BM_RCC_APB1HENR_MDIOSEN         0x20
#define BF_RCC_APB1HENR_MDIOSEN(v)      (((v) & 0x1) << 5)
#define BFM_RCC_APB1HENR_MDIOSEN(v)     BM_RCC_APB1HENR_MDIOSEN
#define BF_RCC_APB1HENR_MDIOSEN_V(e)    BF_RCC_APB1HENR_MDIOSEN(BV_RCC_APB1HENR_MDIOSEN__##e)
#define BFM_RCC_APB1HENR_MDIOSEN_V(v)   BM_RCC_APB1HENR_MDIOSEN
#define BP_RCC_APB1HENR_OPAMPEN         4
#define BM_RCC_APB1HENR_OPAMPEN         0x10
#define BF_RCC_APB1HENR_OPAMPEN(v)      (((v) & 0x1) << 4)
#define BFM_RCC_APB1HENR_OPAMPEN(v)     BM_RCC_APB1HENR_OPAMPEN
#define BF_RCC_APB1HENR_OPAMPEN_V(e)    BF_RCC_APB1HENR_OPAMPEN(BV_RCC_APB1HENR_OPAMPEN__##e)
#define BFM_RCC_APB1HENR_OPAMPEN_V(v)   BM_RCC_APB1HENR_OPAMPEN
#define BP_RCC_APB1HENR_SWPEN           2
#define BM_RCC_APB1HENR_SWPEN           0x4
#define BF_RCC_APB1HENR_SWPEN(v)        (((v) & 0x1) << 2)
#define BFM_RCC_APB1HENR_SWPEN(v)       BM_RCC_APB1HENR_SWPEN
#define BF_RCC_APB1HENR_SWPEN_V(e)      BF_RCC_APB1HENR_SWPEN(BV_RCC_APB1HENR_SWPEN__##e)
#define BFM_RCC_APB1HENR_SWPEN_V(v)     BM_RCC_APB1HENR_SWPEN
#define BP_RCC_APB1HENR_CRSEN           1
#define BM_RCC_APB1HENR_CRSEN           0x2
#define BF_RCC_APB1HENR_CRSEN(v)        (((v) & 0x1) << 1)
#define BFM_RCC_APB1HENR_CRSEN(v)       BM_RCC_APB1HENR_CRSEN
#define BF_RCC_APB1HENR_CRSEN_V(e)      BF_RCC_APB1HENR_CRSEN(BV_RCC_APB1HENR_CRSEN__##e)
#define BFM_RCC_APB1HENR_CRSEN_V(v)     BM_RCC_APB1HENR_CRSEN

#define REG_RCC_APB1HLPENR              st_reg(RCC_APB1HLPENR)
#define STA_RCC_APB1HLPENR              (0x58024400 + 0x114)
#define STO_RCC_APB1HLPENR              (0x114)
#define STT_RCC_APB1HLPENR              STIO_32_RW
#define STN_RCC_APB1HLPENR              RCC_APB1HLPENR
#define BP_RCC_APB1HLPENR_FDCANEN       8
#define BM_RCC_APB1HLPENR_FDCANEN       0x100
#define BF_RCC_APB1HLPENR_FDCANEN(v)    (((v) & 0x1) << 8)
#define BFM_RCC_APB1HLPENR_FDCANEN(v)   BM_RCC_APB1HLPENR_FDCANEN
#define BF_RCC_APB1HLPENR_FDCANEN_V(e)  BF_RCC_APB1HLPENR_FDCANEN(BV_RCC_APB1HLPENR_FDCANEN__##e)
#define BFM_RCC_APB1HLPENR_FDCANEN_V(v) BM_RCC_APB1HLPENR_FDCANEN
#define BP_RCC_APB1HLPENR_MDIOSEN       5
#define BM_RCC_APB1HLPENR_MDIOSEN       0x20
#define BF_RCC_APB1HLPENR_MDIOSEN(v)    (((v) & 0x1) << 5)
#define BFM_RCC_APB1HLPENR_MDIOSEN(v)   BM_RCC_APB1HLPENR_MDIOSEN
#define BF_RCC_APB1HLPENR_MDIOSEN_V(e)  BF_RCC_APB1HLPENR_MDIOSEN(BV_RCC_APB1HLPENR_MDIOSEN__##e)
#define BFM_RCC_APB1HLPENR_MDIOSEN_V(v) BM_RCC_APB1HLPENR_MDIOSEN
#define BP_RCC_APB1HLPENR_OPAMPEN       4
#define BM_RCC_APB1HLPENR_OPAMPEN       0x10
#define BF_RCC_APB1HLPENR_OPAMPEN(v)    (((v) & 0x1) << 4)
#define BFM_RCC_APB1HLPENR_OPAMPEN(v)   BM_RCC_APB1HLPENR_OPAMPEN
#define BF_RCC_APB1HLPENR_OPAMPEN_V(e)  BF_RCC_APB1HLPENR_OPAMPEN(BV_RCC_APB1HLPENR_OPAMPEN__##e)
#define BFM_RCC_APB1HLPENR_OPAMPEN_V(v) BM_RCC_APB1HLPENR_OPAMPEN
#define BP_RCC_APB1HLPENR_SWPEN         2
#define BM_RCC_APB1HLPENR_SWPEN         0x4
#define BF_RCC_APB1HLPENR_SWPEN(v)      (((v) & 0x1) << 2)
#define BFM_RCC_APB1HLPENR_SWPEN(v)     BM_RCC_APB1HLPENR_SWPEN
#define BF_RCC_APB1HLPENR_SWPEN_V(e)    BF_RCC_APB1HLPENR_SWPEN(BV_RCC_APB1HLPENR_SWPEN__##e)
#define BFM_RCC_APB1HLPENR_SWPEN_V(v)   BM_RCC_APB1HLPENR_SWPEN
#define BP_RCC_APB1HLPENR_CRSEN         1
#define BM_RCC_APB1HLPENR_CRSEN         0x2
#define BF_RCC_APB1HLPENR_CRSEN(v)      (((v) & 0x1) << 1)
#define BFM_RCC_APB1HLPENR_CRSEN(v)     BM_RCC_APB1HLPENR_CRSEN
#define BF_RCC_APB1HLPENR_CRSEN_V(e)    BF_RCC_APB1HLPENR_CRSEN(BV_RCC_APB1HLPENR_CRSEN__##e)
#define BFM_RCC_APB1HLPENR_CRSEN_V(v)   BM_RCC_APB1HLPENR_CRSEN

#define REG_RCC_APB2ENR                 st_reg(RCC_APB2ENR)
#define STA_RCC_APB2ENR                 (0x58024400 + 0xf0)
#define STO_RCC_APB2ENR                 (0xf0)
#define STT_RCC_APB2ENR                 STIO_32_RW
#define STN_RCC_APB2ENR                 RCC_APB2ENR
#define BP_RCC_APB2ENR_HRTIMEN          29
#define BM_RCC_APB2ENR_HRTIMEN          0x20000000
#define BF_RCC_APB2ENR_HRTIMEN(v)       (((v) & 0x1) << 29)
#define BFM_RCC_APB2ENR_HRTIMEN(v)      BM_RCC_APB2ENR_HRTIMEN
#define BF_RCC_APB2ENR_HRTIMEN_V(e)     BF_RCC_APB2ENR_HRTIMEN(BV_RCC_APB2ENR_HRTIMEN__##e)
#define BFM_RCC_APB2ENR_HRTIMEN_V(v)    BM_RCC_APB2ENR_HRTIMEN
#define BP_RCC_APB2ENR_DFSDM1EN         28
#define BM_RCC_APB2ENR_DFSDM1EN         0x10000000
#define BF_RCC_APB2ENR_DFSDM1EN(v)      (((v) & 0x1) << 28)
#define BFM_RCC_APB2ENR_DFSDM1EN(v)     BM_RCC_APB2ENR_DFSDM1EN
#define BF_RCC_APB2ENR_DFSDM1EN_V(e)    BF_RCC_APB2ENR_DFSDM1EN(BV_RCC_APB2ENR_DFSDM1EN__##e)
#define BFM_RCC_APB2ENR_DFSDM1EN_V(v)   BM_RCC_APB2ENR_DFSDM1EN
#define BP_RCC_APB2ENR_SAI3EN           24
#define BM_RCC_APB2ENR_SAI3EN           0x1000000
#define BF_RCC_APB2ENR_SAI3EN(v)        (((v) & 0x1) << 24)
#define BFM_RCC_APB2ENR_SAI3EN(v)       BM_RCC_APB2ENR_SAI3EN
#define BF_RCC_APB2ENR_SAI3EN_V(e)      BF_RCC_APB2ENR_SAI3EN(BV_RCC_APB2ENR_SAI3EN__##e)
#define BFM_RCC_APB2ENR_SAI3EN_V(v)     BM_RCC_APB2ENR_SAI3EN
#define BP_RCC_APB2ENR_SAI2EN           23
#define BM_RCC_APB2ENR_SAI2EN           0x800000
#define BF_RCC_APB2ENR_SAI2EN(v)        (((v) & 0x1) << 23)
#define BFM_RCC_APB2ENR_SAI2EN(v)       BM_RCC_APB2ENR_SAI2EN
#define BF_RCC_APB2ENR_SAI2EN_V(e)      BF_RCC_APB2ENR_SAI2EN(BV_RCC_APB2ENR_SAI2EN__##e)
#define BFM_RCC_APB2ENR_SAI2EN_V(v)     BM_RCC_APB2ENR_SAI2EN
#define BP_RCC_APB2ENR_SAI1EN           22
#define BM_RCC_APB2ENR_SAI1EN           0x400000
#define BF_RCC_APB2ENR_SAI1EN(v)        (((v) & 0x1) << 22)
#define BFM_RCC_APB2ENR_SAI1EN(v)       BM_RCC_APB2ENR_SAI1EN
#define BF_RCC_APB2ENR_SAI1EN_V(e)      BF_RCC_APB2ENR_SAI1EN(BV_RCC_APB2ENR_SAI1EN__##e)
#define BFM_RCC_APB2ENR_SAI1EN_V(v)     BM_RCC_APB2ENR_SAI1EN
#define BP_RCC_APB2ENR_SPI5EN           20
#define BM_RCC_APB2ENR_SPI5EN           0x100000
#define BF_RCC_APB2ENR_SPI5EN(v)        (((v) & 0x1) << 20)
#define BFM_RCC_APB2ENR_SPI5EN(v)       BM_RCC_APB2ENR_SPI5EN
#define BF_RCC_APB2ENR_SPI5EN_V(e)      BF_RCC_APB2ENR_SPI5EN(BV_RCC_APB2ENR_SPI5EN__##e)
#define BFM_RCC_APB2ENR_SPI5EN_V(v)     BM_RCC_APB2ENR_SPI5EN
#define BP_RCC_APB2ENR_TIM17EN          18
#define BM_RCC_APB2ENR_TIM17EN          0x40000
#define BF_RCC_APB2ENR_TIM17EN(v)       (((v) & 0x1) << 18)
#define BFM_RCC_APB2ENR_TIM17EN(v)      BM_RCC_APB2ENR_TIM17EN
#define BF_RCC_APB2ENR_TIM17EN_V(e)     BF_RCC_APB2ENR_TIM17EN(BV_RCC_APB2ENR_TIM17EN__##e)
#define BFM_RCC_APB2ENR_TIM17EN_V(v)    BM_RCC_APB2ENR_TIM17EN
#define BP_RCC_APB2ENR_TIM16EN          17
#define BM_RCC_APB2ENR_TIM16EN          0x20000
#define BF_RCC_APB2ENR_TIM16EN(v)       (((v) & 0x1) << 17)
#define BFM_RCC_APB2ENR_TIM16EN(v)      BM_RCC_APB2ENR_TIM16EN
#define BF_RCC_APB2ENR_TIM16EN_V(e)     BF_RCC_APB2ENR_TIM16EN(BV_RCC_APB2ENR_TIM16EN__##e)
#define BFM_RCC_APB2ENR_TIM16EN_V(v)    BM_RCC_APB2ENR_TIM16EN
#define BP_RCC_APB2ENR_TIM15EN          16
#define BM_RCC_APB2ENR_TIM15EN          0x10000
#define BF_RCC_APB2ENR_TIM15EN(v)       (((v) & 0x1) << 16)
#define BFM_RCC_APB2ENR_TIM15EN(v)      BM_RCC_APB2ENR_TIM15EN
#define BF_RCC_APB2ENR_TIM15EN_V(e)     BF_RCC_APB2ENR_TIM15EN(BV_RCC_APB2ENR_TIM15EN__##e)
#define BFM_RCC_APB2ENR_TIM15EN_V(v)    BM_RCC_APB2ENR_TIM15EN
#define BP_RCC_APB2ENR_SPI4EN           13
#define BM_RCC_APB2ENR_SPI4EN           0x2000
#define BF_RCC_APB2ENR_SPI4EN(v)        (((v) & 0x1) << 13)
#define BFM_RCC_APB2ENR_SPI4EN(v)       BM_RCC_APB2ENR_SPI4EN
#define BF_RCC_APB2ENR_SPI4EN_V(e)      BF_RCC_APB2ENR_SPI4EN(BV_RCC_APB2ENR_SPI4EN__##e)
#define BFM_RCC_APB2ENR_SPI4EN_V(v)     BM_RCC_APB2ENR_SPI4EN
#define BP_RCC_APB2ENR_SPI1EN           12
#define BM_RCC_APB2ENR_SPI1EN           0x1000
#define BF_RCC_APB2ENR_SPI1EN(v)        (((v) & 0x1) << 12)
#define BFM_RCC_APB2ENR_SPI1EN(v)       BM_RCC_APB2ENR_SPI1EN
#define BF_RCC_APB2ENR_SPI1EN_V(e)      BF_RCC_APB2ENR_SPI1EN(BV_RCC_APB2ENR_SPI1EN__##e)
#define BFM_RCC_APB2ENR_SPI1EN_V(v)     BM_RCC_APB2ENR_SPI1EN
#define BP_RCC_APB2ENR_USART6EN         5
#define BM_RCC_APB2ENR_USART6EN         0x20
#define BF_RCC_APB2ENR_USART6EN(v)      (((v) & 0x1) << 5)
#define BFM_RCC_APB2ENR_USART6EN(v)     BM_RCC_APB2ENR_USART6EN
#define BF_RCC_APB2ENR_USART6EN_V(e)    BF_RCC_APB2ENR_USART6EN(BV_RCC_APB2ENR_USART6EN__##e)
#define BFM_RCC_APB2ENR_USART6EN_V(v)   BM_RCC_APB2ENR_USART6EN
#define BP_RCC_APB2ENR_USART1EN         4
#define BM_RCC_APB2ENR_USART1EN         0x10
#define BF_RCC_APB2ENR_USART1EN(v)      (((v) & 0x1) << 4)
#define BFM_RCC_APB2ENR_USART1EN(v)     BM_RCC_APB2ENR_USART1EN
#define BF_RCC_APB2ENR_USART1EN_V(e)    BF_RCC_APB2ENR_USART1EN(BV_RCC_APB2ENR_USART1EN__##e)
#define BFM_RCC_APB2ENR_USART1EN_V(v)   BM_RCC_APB2ENR_USART1EN
#define BP_RCC_APB2ENR_TIM8EN           1
#define BM_RCC_APB2ENR_TIM8EN           0x2
#define BF_RCC_APB2ENR_TIM8EN(v)        (((v) & 0x1) << 1)
#define BFM_RCC_APB2ENR_TIM8EN(v)       BM_RCC_APB2ENR_TIM8EN
#define BF_RCC_APB2ENR_TIM8EN_V(e)      BF_RCC_APB2ENR_TIM8EN(BV_RCC_APB2ENR_TIM8EN__##e)
#define BFM_RCC_APB2ENR_TIM8EN_V(v)     BM_RCC_APB2ENR_TIM8EN
#define BP_RCC_APB2ENR_TIM1EN           0
#define BM_RCC_APB2ENR_TIM1EN           0x1
#define BF_RCC_APB2ENR_TIM1EN(v)        (((v) & 0x1) << 0)
#define BFM_RCC_APB2ENR_TIM1EN(v)       BM_RCC_APB2ENR_TIM1EN
#define BF_RCC_APB2ENR_TIM1EN_V(e)      BF_RCC_APB2ENR_TIM1EN(BV_RCC_APB2ENR_TIM1EN__##e)
#define BFM_RCC_APB2ENR_TIM1EN_V(v)     BM_RCC_APB2ENR_TIM1EN

#define REG_RCC_APB2LPENR               st_reg(RCC_APB2LPENR)
#define STA_RCC_APB2LPENR               (0x58024400 + 0x118)
#define STO_RCC_APB2LPENR               (0x118)
#define STT_RCC_APB2LPENR               STIO_32_RW
#define STN_RCC_APB2LPENR               RCC_APB2LPENR
#define BP_RCC_APB2LPENR_HRTIMEN        29
#define BM_RCC_APB2LPENR_HRTIMEN        0x20000000
#define BF_RCC_APB2LPENR_HRTIMEN(v)     (((v) & 0x1) << 29)
#define BFM_RCC_APB2LPENR_HRTIMEN(v)    BM_RCC_APB2LPENR_HRTIMEN
#define BF_RCC_APB2LPENR_HRTIMEN_V(e)   BF_RCC_APB2LPENR_HRTIMEN(BV_RCC_APB2LPENR_HRTIMEN__##e)
#define BFM_RCC_APB2LPENR_HRTIMEN_V(v)  BM_RCC_APB2LPENR_HRTIMEN
#define BP_RCC_APB2LPENR_DFSDM1EN       28
#define BM_RCC_APB2LPENR_DFSDM1EN       0x10000000
#define BF_RCC_APB2LPENR_DFSDM1EN(v)    (((v) & 0x1) << 28)
#define BFM_RCC_APB2LPENR_DFSDM1EN(v)   BM_RCC_APB2LPENR_DFSDM1EN
#define BF_RCC_APB2LPENR_DFSDM1EN_V(e)  BF_RCC_APB2LPENR_DFSDM1EN(BV_RCC_APB2LPENR_DFSDM1EN__##e)
#define BFM_RCC_APB2LPENR_DFSDM1EN_V(v) BM_RCC_APB2LPENR_DFSDM1EN
#define BP_RCC_APB2LPENR_SAI3EN         24
#define BM_RCC_APB2LPENR_SAI3EN         0x1000000
#define BF_RCC_APB2LPENR_SAI3EN(v)      (((v) & 0x1) << 24)
#define BFM_RCC_APB2LPENR_SAI3EN(v)     BM_RCC_APB2LPENR_SAI3EN
#define BF_RCC_APB2LPENR_SAI3EN_V(e)    BF_RCC_APB2LPENR_SAI3EN(BV_RCC_APB2LPENR_SAI3EN__##e)
#define BFM_RCC_APB2LPENR_SAI3EN_V(v)   BM_RCC_APB2LPENR_SAI3EN
#define BP_RCC_APB2LPENR_SAI2EN         23
#define BM_RCC_APB2LPENR_SAI2EN         0x800000
#define BF_RCC_APB2LPENR_SAI2EN(v)      (((v) & 0x1) << 23)
#define BFM_RCC_APB2LPENR_SAI2EN(v)     BM_RCC_APB2LPENR_SAI2EN
#define BF_RCC_APB2LPENR_SAI2EN_V(e)    BF_RCC_APB2LPENR_SAI2EN(BV_RCC_APB2LPENR_SAI2EN__##e)
#define BFM_RCC_APB2LPENR_SAI2EN_V(v)   BM_RCC_APB2LPENR_SAI2EN
#define BP_RCC_APB2LPENR_SAI1EN         22
#define BM_RCC_APB2LPENR_SAI1EN         0x400000
#define BF_RCC_APB2LPENR_SAI1EN(v)      (((v) & 0x1) << 22)
#define BFM_RCC_APB2LPENR_SAI1EN(v)     BM_RCC_APB2LPENR_SAI1EN
#define BF_RCC_APB2LPENR_SAI1EN_V(e)    BF_RCC_APB2LPENR_SAI1EN(BV_RCC_APB2LPENR_SAI1EN__##e)
#define BFM_RCC_APB2LPENR_SAI1EN_V(v)   BM_RCC_APB2LPENR_SAI1EN
#define BP_RCC_APB2LPENR_SPI5EN         20
#define BM_RCC_APB2LPENR_SPI5EN         0x100000
#define BF_RCC_APB2LPENR_SPI5EN(v)      (((v) & 0x1) << 20)
#define BFM_RCC_APB2LPENR_SPI5EN(v)     BM_RCC_APB2LPENR_SPI5EN
#define BF_RCC_APB2LPENR_SPI5EN_V(e)    BF_RCC_APB2LPENR_SPI5EN(BV_RCC_APB2LPENR_SPI5EN__##e)
#define BFM_RCC_APB2LPENR_SPI5EN_V(v)   BM_RCC_APB2LPENR_SPI5EN
#define BP_RCC_APB2LPENR_TIM17EN        18
#define BM_RCC_APB2LPENR_TIM17EN        0x40000
#define BF_RCC_APB2LPENR_TIM17EN(v)     (((v) & 0x1) << 18)
#define BFM_RCC_APB2LPENR_TIM17EN(v)    BM_RCC_APB2LPENR_TIM17EN
#define BF_RCC_APB2LPENR_TIM17EN_V(e)   BF_RCC_APB2LPENR_TIM17EN(BV_RCC_APB2LPENR_TIM17EN__##e)
#define BFM_RCC_APB2LPENR_TIM17EN_V(v)  BM_RCC_APB2LPENR_TIM17EN
#define BP_RCC_APB2LPENR_TIM16EN        17
#define BM_RCC_APB2LPENR_TIM16EN        0x20000
#define BF_RCC_APB2LPENR_TIM16EN(v)     (((v) & 0x1) << 17)
#define BFM_RCC_APB2LPENR_TIM16EN(v)    BM_RCC_APB2LPENR_TIM16EN
#define BF_RCC_APB2LPENR_TIM16EN_V(e)   BF_RCC_APB2LPENR_TIM16EN(BV_RCC_APB2LPENR_TIM16EN__##e)
#define BFM_RCC_APB2LPENR_TIM16EN_V(v)  BM_RCC_APB2LPENR_TIM16EN
#define BP_RCC_APB2LPENR_TIM15EN        16
#define BM_RCC_APB2LPENR_TIM15EN        0x10000
#define BF_RCC_APB2LPENR_TIM15EN(v)     (((v) & 0x1) << 16)
#define BFM_RCC_APB2LPENR_TIM15EN(v)    BM_RCC_APB2LPENR_TIM15EN
#define BF_RCC_APB2LPENR_TIM15EN_V(e)   BF_RCC_APB2LPENR_TIM15EN(BV_RCC_APB2LPENR_TIM15EN__##e)
#define BFM_RCC_APB2LPENR_TIM15EN_V(v)  BM_RCC_APB2LPENR_TIM15EN
#define BP_RCC_APB2LPENR_SPI4EN         13
#define BM_RCC_APB2LPENR_SPI4EN         0x2000
#define BF_RCC_APB2LPENR_SPI4EN(v)      (((v) & 0x1) << 13)
#define BFM_RCC_APB2LPENR_SPI4EN(v)     BM_RCC_APB2LPENR_SPI4EN
#define BF_RCC_APB2LPENR_SPI4EN_V(e)    BF_RCC_APB2LPENR_SPI4EN(BV_RCC_APB2LPENR_SPI4EN__##e)
#define BFM_RCC_APB2LPENR_SPI4EN_V(v)   BM_RCC_APB2LPENR_SPI4EN
#define BP_RCC_APB2LPENR_SPI1EN         12
#define BM_RCC_APB2LPENR_SPI1EN         0x1000
#define BF_RCC_APB2LPENR_SPI1EN(v)      (((v) & 0x1) << 12)
#define BFM_RCC_APB2LPENR_SPI1EN(v)     BM_RCC_APB2LPENR_SPI1EN
#define BF_RCC_APB2LPENR_SPI1EN_V(e)    BF_RCC_APB2LPENR_SPI1EN(BV_RCC_APB2LPENR_SPI1EN__##e)
#define BFM_RCC_APB2LPENR_SPI1EN_V(v)   BM_RCC_APB2LPENR_SPI1EN
#define BP_RCC_APB2LPENR_USART6EN       5
#define BM_RCC_APB2LPENR_USART6EN       0x20
#define BF_RCC_APB2LPENR_USART6EN(v)    (((v) & 0x1) << 5)
#define BFM_RCC_APB2LPENR_USART6EN(v)   BM_RCC_APB2LPENR_USART6EN
#define BF_RCC_APB2LPENR_USART6EN_V(e)  BF_RCC_APB2LPENR_USART6EN(BV_RCC_APB2LPENR_USART6EN__##e)
#define BFM_RCC_APB2LPENR_USART6EN_V(v) BM_RCC_APB2LPENR_USART6EN
#define BP_RCC_APB2LPENR_USART1EN       4
#define BM_RCC_APB2LPENR_USART1EN       0x10
#define BF_RCC_APB2LPENR_USART1EN(v)    (((v) & 0x1) << 4)
#define BFM_RCC_APB2LPENR_USART1EN(v)   BM_RCC_APB2LPENR_USART1EN
#define BF_RCC_APB2LPENR_USART1EN_V(e)  BF_RCC_APB2LPENR_USART1EN(BV_RCC_APB2LPENR_USART1EN__##e)
#define BFM_RCC_APB2LPENR_USART1EN_V(v) BM_RCC_APB2LPENR_USART1EN
#define BP_RCC_APB2LPENR_TIM8EN         1
#define BM_RCC_APB2LPENR_TIM8EN         0x2
#define BF_RCC_APB2LPENR_TIM8EN(v)      (((v) & 0x1) << 1)
#define BFM_RCC_APB2LPENR_TIM8EN(v)     BM_RCC_APB2LPENR_TIM8EN
#define BF_RCC_APB2LPENR_TIM8EN_V(e)    BF_RCC_APB2LPENR_TIM8EN(BV_RCC_APB2LPENR_TIM8EN__##e)
#define BFM_RCC_APB2LPENR_TIM8EN_V(v)   BM_RCC_APB2LPENR_TIM8EN
#define BP_RCC_APB2LPENR_TIM1EN         0
#define BM_RCC_APB2LPENR_TIM1EN         0x1
#define BF_RCC_APB2LPENR_TIM1EN(v)      (((v) & 0x1) << 0)
#define BFM_RCC_APB2LPENR_TIM1EN(v)     BM_RCC_APB2LPENR_TIM1EN
#define BF_RCC_APB2LPENR_TIM1EN_V(e)    BF_RCC_APB2LPENR_TIM1EN(BV_RCC_APB2LPENR_TIM1EN__##e)
#define BFM_RCC_APB2LPENR_TIM1EN_V(v)   BM_RCC_APB2LPENR_TIM1EN

#define REG_RCC_APB4ENR                 st_reg(RCC_APB4ENR)
#define STA_RCC_APB4ENR                 (0x58024400 + 0xf4)
#define STO_RCC_APB4ENR                 (0xf4)
#define STT_RCC_APB4ENR                 STIO_32_RW
#define STN_RCC_APB4ENR                 RCC_APB4ENR
#define BP_RCC_APB4ENR_SAI4EN           21
#define BM_RCC_APB4ENR_SAI4EN           0x200000
#define BF_RCC_APB4ENR_SAI4EN(v)        (((v) & 0x1) << 21)
#define BFM_RCC_APB4ENR_SAI4EN(v)       BM_RCC_APB4ENR_SAI4EN
#define BF_RCC_APB4ENR_SAI4EN_V(e)      BF_RCC_APB4ENR_SAI4EN(BV_RCC_APB4ENR_SAI4EN__##e)
#define BFM_RCC_APB4ENR_SAI4EN_V(v)     BM_RCC_APB4ENR_SAI4EN
#define BP_RCC_APB4ENR_RTCAPBEN         16
#define BM_RCC_APB4ENR_RTCAPBEN         0x10000
#define BF_RCC_APB4ENR_RTCAPBEN(v)      (((v) & 0x1) << 16)
#define BFM_RCC_APB4ENR_RTCAPBEN(v)     BM_RCC_APB4ENR_RTCAPBEN
#define BF_RCC_APB4ENR_RTCAPBEN_V(e)    BF_RCC_APB4ENR_RTCAPBEN(BV_RCC_APB4ENR_RTCAPBEN__##e)
#define BFM_RCC_APB4ENR_RTCAPBEN_V(v)   BM_RCC_APB4ENR_RTCAPBEN
#define BP_RCC_APB4ENR_VREFEN           15
#define BM_RCC_APB4ENR_VREFEN           0x8000
#define BF_RCC_APB4ENR_VREFEN(v)        (((v) & 0x1) << 15)
#define BFM_RCC_APB4ENR_VREFEN(v)       BM_RCC_APB4ENR_VREFEN
#define BF_RCC_APB4ENR_VREFEN_V(e)      BF_RCC_APB4ENR_VREFEN(BV_RCC_APB4ENR_VREFEN__##e)
#define BFM_RCC_APB4ENR_VREFEN_V(v)     BM_RCC_APB4ENR_VREFEN
#define BP_RCC_APB4ENR_COMP12EN         14
#define BM_RCC_APB4ENR_COMP12EN         0x4000
#define BF_RCC_APB4ENR_COMP12EN(v)      (((v) & 0x1) << 14)
#define BFM_RCC_APB4ENR_COMP12EN(v)     BM_RCC_APB4ENR_COMP12EN
#define BF_RCC_APB4ENR_COMP12EN_V(e)    BF_RCC_APB4ENR_COMP12EN(BV_RCC_APB4ENR_COMP12EN__##e)
#define BFM_RCC_APB4ENR_COMP12EN_V(v)   BM_RCC_APB4ENR_COMP12EN
#define BP_RCC_APB4ENR_LPTIM5EN         12
#define BM_RCC_APB4ENR_LPTIM5EN         0x1000
#define BF_RCC_APB4ENR_LPTIM5EN(v)      (((v) & 0x1) << 12)
#define BFM_RCC_APB4ENR_LPTIM5EN(v)     BM_RCC_APB4ENR_LPTIM5EN
#define BF_RCC_APB4ENR_LPTIM5EN_V(e)    BF_RCC_APB4ENR_LPTIM5EN(BV_RCC_APB4ENR_LPTIM5EN__##e)
#define BFM_RCC_APB4ENR_LPTIM5EN_V(v)   BM_RCC_APB4ENR_LPTIM5EN
#define BP_RCC_APB4ENR_LPTIM4EN         11
#define BM_RCC_APB4ENR_LPTIM4EN         0x800
#define BF_RCC_APB4ENR_LPTIM4EN(v)      (((v) & 0x1) << 11)
#define BFM_RCC_APB4ENR_LPTIM4EN(v)     BM_RCC_APB4ENR_LPTIM4EN
#define BF_RCC_APB4ENR_LPTIM4EN_V(e)    BF_RCC_APB4ENR_LPTIM4EN(BV_RCC_APB4ENR_LPTIM4EN__##e)
#define BFM_RCC_APB4ENR_LPTIM4EN_V(v)   BM_RCC_APB4ENR_LPTIM4EN
#define BP_RCC_APB4ENR_LPTIM3EN         10
#define BM_RCC_APB4ENR_LPTIM3EN         0x400
#define BF_RCC_APB4ENR_LPTIM3EN(v)      (((v) & 0x1) << 10)
#define BFM_RCC_APB4ENR_LPTIM3EN(v)     BM_RCC_APB4ENR_LPTIM3EN
#define BF_RCC_APB4ENR_LPTIM3EN_V(e)    BF_RCC_APB4ENR_LPTIM3EN(BV_RCC_APB4ENR_LPTIM3EN__##e)
#define BFM_RCC_APB4ENR_LPTIM3EN_V(v)   BM_RCC_APB4ENR_LPTIM3EN
#define BP_RCC_APB4ENR_LPTIM2EN         9
#define BM_RCC_APB4ENR_LPTIM2EN         0x200
#define BF_RCC_APB4ENR_LPTIM2EN(v)      (((v) & 0x1) << 9)
#define BFM_RCC_APB4ENR_LPTIM2EN(v)     BM_RCC_APB4ENR_LPTIM2EN
#define BF_RCC_APB4ENR_LPTIM2EN_V(e)    BF_RCC_APB4ENR_LPTIM2EN(BV_RCC_APB4ENR_LPTIM2EN__##e)
#define BFM_RCC_APB4ENR_LPTIM2EN_V(v)   BM_RCC_APB4ENR_LPTIM2EN
#define BP_RCC_APB4ENR_I2C4EN           7
#define BM_RCC_APB4ENR_I2C4EN           0x80
#define BF_RCC_APB4ENR_I2C4EN(v)        (((v) & 0x1) << 7)
#define BFM_RCC_APB4ENR_I2C4EN(v)       BM_RCC_APB4ENR_I2C4EN
#define BF_RCC_APB4ENR_I2C4EN_V(e)      BF_RCC_APB4ENR_I2C4EN(BV_RCC_APB4ENR_I2C4EN__##e)
#define BFM_RCC_APB4ENR_I2C4EN_V(v)     BM_RCC_APB4ENR_I2C4EN
#define BP_RCC_APB4ENR_SPI6EN           5
#define BM_RCC_APB4ENR_SPI6EN           0x20
#define BF_RCC_APB4ENR_SPI6EN(v)        (((v) & 0x1) << 5)
#define BFM_RCC_APB4ENR_SPI6EN(v)       BM_RCC_APB4ENR_SPI6EN
#define BF_RCC_APB4ENR_SPI6EN_V(e)      BF_RCC_APB4ENR_SPI6EN(BV_RCC_APB4ENR_SPI6EN__##e)
#define BFM_RCC_APB4ENR_SPI6EN_V(v)     BM_RCC_APB4ENR_SPI6EN
#define BP_RCC_APB4ENR_LPUART1EN        3
#define BM_RCC_APB4ENR_LPUART1EN        0x8
#define BF_RCC_APB4ENR_LPUART1EN(v)     (((v) & 0x1) << 3)
#define BFM_RCC_APB4ENR_LPUART1EN(v)    BM_RCC_APB4ENR_LPUART1EN
#define BF_RCC_APB4ENR_LPUART1EN_V(e)   BF_RCC_APB4ENR_LPUART1EN(BV_RCC_APB4ENR_LPUART1EN__##e)
#define BFM_RCC_APB4ENR_LPUART1EN_V(v)  BM_RCC_APB4ENR_LPUART1EN
#define BP_RCC_APB4ENR_SYSCFGEN         1
#define BM_RCC_APB4ENR_SYSCFGEN         0x2
#define BF_RCC_APB4ENR_SYSCFGEN(v)      (((v) & 0x1) << 1)
#define BFM_RCC_APB4ENR_SYSCFGEN(v)     BM_RCC_APB4ENR_SYSCFGEN
#define BF_RCC_APB4ENR_SYSCFGEN_V(e)    BF_RCC_APB4ENR_SYSCFGEN(BV_RCC_APB4ENR_SYSCFGEN__##e)
#define BFM_RCC_APB4ENR_SYSCFGEN_V(v)   BM_RCC_APB4ENR_SYSCFGEN

#define REG_RCC_APB4LPENR                   st_reg(RCC_APB4LPENR)
#define STA_RCC_APB4LPENR                   (0x58024400 + 0x11c)
#define STO_RCC_APB4LPENR                   (0x11c)
#define STT_RCC_APB4LPENR                   STIO_32_RW
#define STN_RCC_APB4LPENR                   RCC_APB4LPENR
#define BP_RCC_APB4LPENR_SAI4EN             21
#define BM_RCC_APB4LPENR_SAI4EN             0x200000
#define BF_RCC_APB4LPENR_SAI4EN(v)          (((v) & 0x1) << 21)
#define BFM_RCC_APB4LPENR_SAI4EN(v)         BM_RCC_APB4LPENR_SAI4EN
#define BF_RCC_APB4LPENR_SAI4EN_V(e)        BF_RCC_APB4LPENR_SAI4EN(BV_RCC_APB4LPENR_SAI4EN__##e)
#define BFM_RCC_APB4LPENR_SAI4EN_V(v)       BM_RCC_APB4LPENR_SAI4EN
#define BP_RCC_APB4LPENR_RTCAPBEN           16
#define BM_RCC_APB4LPENR_RTCAPBEN           0x10000
#define BF_RCC_APB4LPENR_RTCAPBEN(v)        (((v) & 0x1) << 16)
#define BFM_RCC_APB4LPENR_RTCAPBEN(v)       BM_RCC_APB4LPENR_RTCAPBEN
#define BF_RCC_APB4LPENR_RTCAPBEN_V(e)      BF_RCC_APB4LPENR_RTCAPBEN(BV_RCC_APB4LPENR_RTCAPBEN__##e)
#define BFM_RCC_APB4LPENR_RTCAPBEN_V(v)     BM_RCC_APB4LPENR_RTCAPBEN
#define BP_RCC_APB4LPENR_VREFEN             15
#define BM_RCC_APB4LPENR_VREFEN             0x8000
#define BF_RCC_APB4LPENR_VREFEN(v)          (((v) & 0x1) << 15)
#define BFM_RCC_APB4LPENR_VREFEN(v)         BM_RCC_APB4LPENR_VREFEN
#define BF_RCC_APB4LPENR_VREFEN_V(e)        BF_RCC_APB4LPENR_VREFEN(BV_RCC_APB4LPENR_VREFEN__##e)
#define BFM_RCC_APB4LPENR_VREFEN_V(v)       BM_RCC_APB4LPENR_VREFEN
#define BP_RCC_APB4LPENR_COMP12EN           14
#define BM_RCC_APB4LPENR_COMP12EN           0x4000
#define BF_RCC_APB4LPENR_COMP12EN(v)        (((v) & 0x1) << 14)
#define BFM_RCC_APB4LPENR_COMP12EN(v)       BM_RCC_APB4LPENR_COMP12EN
#define BF_RCC_APB4LPENR_COMP12EN_V(e)      BF_RCC_APB4LPENR_COMP12EN(BV_RCC_APB4LPENR_COMP12EN__##e)
#define BFM_RCC_APB4LPENR_COMP12EN_V(v)     BM_RCC_APB4LPENR_COMP12EN
#define BP_RCC_APB4LPENR_LPTIM5EN           12
#define BM_RCC_APB4LPENR_LPTIM5EN           0x1000
#define BF_RCC_APB4LPENR_LPTIM5EN(v)        (((v) & 0x1) << 12)
#define BFM_RCC_APB4LPENR_LPTIM5EN(v)       BM_RCC_APB4LPENR_LPTIM5EN
#define BF_RCC_APB4LPENR_LPTIM5EN_V(e)      BF_RCC_APB4LPENR_LPTIM5EN(BV_RCC_APB4LPENR_LPTIM5EN__##e)
#define BFM_RCC_APB4LPENR_LPTIM5EN_V(v)     BM_RCC_APB4LPENR_LPTIM5EN
#define BP_RCC_APB4LPENR_LPTIM4EN           11
#define BM_RCC_APB4LPENR_LPTIM4EN           0x800
#define BF_RCC_APB4LPENR_LPTIM4EN(v)        (((v) & 0x1) << 11)
#define BFM_RCC_APB4LPENR_LPTIM4EN(v)       BM_RCC_APB4LPENR_LPTIM4EN
#define BF_RCC_APB4LPENR_LPTIM4EN_V(e)      BF_RCC_APB4LPENR_LPTIM4EN(BV_RCC_APB4LPENR_LPTIM4EN__##e)
#define BFM_RCC_APB4LPENR_LPTIM4EN_V(v)     BM_RCC_APB4LPENR_LPTIM4EN
#define BP_RCC_APB4LPENR_LPTIM3EN           10
#define BM_RCC_APB4LPENR_LPTIM3EN           0x400
#define BF_RCC_APB4LPENR_LPTIM3EN(v)        (((v) & 0x1) << 10)
#define BFM_RCC_APB4LPENR_LPTIM3EN(v)       BM_RCC_APB4LPENR_LPTIM3EN
#define BF_RCC_APB4LPENR_LPTIM3EN_V(e)      BF_RCC_APB4LPENR_LPTIM3EN(BV_RCC_APB4LPENR_LPTIM3EN__##e)
#define BFM_RCC_APB4LPENR_LPTIM3EN_V(v)     BM_RCC_APB4LPENR_LPTIM3EN
#define BP_RCC_APB4LPENR_LPTIM2EN           9
#define BM_RCC_APB4LPENR_LPTIM2EN           0x200
#define BF_RCC_APB4LPENR_LPTIM2EN(v)        (((v) & 0x1) << 9)
#define BFM_RCC_APB4LPENR_LPTIM2EN(v)       BM_RCC_APB4LPENR_LPTIM2EN
#define BF_RCC_APB4LPENR_LPTIM2EN_V(e)      BF_RCC_APB4LPENR_LPTIM2EN(BV_RCC_APB4LPENR_LPTIM2EN__##e)
#define BFM_RCC_APB4LPENR_LPTIM2EN_V(v)     BM_RCC_APB4LPENR_LPTIM2EN
#define BP_RCC_APB4LPENR_I2C4EN             7
#define BM_RCC_APB4LPENR_I2C4EN             0x80
#define BF_RCC_APB4LPENR_I2C4EN(v)          (((v) & 0x1) << 7)
#define BFM_RCC_APB4LPENR_I2C4EN(v)         BM_RCC_APB4LPENR_I2C4EN
#define BF_RCC_APB4LPENR_I2C4EN_V(e)        BF_RCC_APB4LPENR_I2C4EN(BV_RCC_APB4LPENR_I2C4EN__##e)
#define BFM_RCC_APB4LPENR_I2C4EN_V(v)       BM_RCC_APB4LPENR_I2C4EN
#define BP_RCC_APB4LPENR_SPI6EN             5
#define BM_RCC_APB4LPENR_SPI6EN             0x20
#define BF_RCC_APB4LPENR_SPI6EN(v)          (((v) & 0x1) << 5)
#define BFM_RCC_APB4LPENR_SPI6EN(v)         BM_RCC_APB4LPENR_SPI6EN
#define BF_RCC_APB4LPENR_SPI6EN_V(e)        BF_RCC_APB4LPENR_SPI6EN(BV_RCC_APB4LPENR_SPI6EN__##e)
#define BFM_RCC_APB4LPENR_SPI6EN_V(v)       BM_RCC_APB4LPENR_SPI6EN
#define BP_RCC_APB4LPENR_LPUART1EN          3
#define BM_RCC_APB4LPENR_LPUART1EN          0x8
#define BF_RCC_APB4LPENR_LPUART1EN(v)       (((v) & 0x1) << 3)
#define BFM_RCC_APB4LPENR_LPUART1EN(v)      BM_RCC_APB4LPENR_LPUART1EN
#define BF_RCC_APB4LPENR_LPUART1EN_V(e)     BF_RCC_APB4LPENR_LPUART1EN(BV_RCC_APB4LPENR_LPUART1EN__##e)
#define BFM_RCC_APB4LPENR_LPUART1EN_V(v)    BM_RCC_APB4LPENR_LPUART1EN
#define BP_RCC_APB4LPENR_SYSCFGEN           1
#define BM_RCC_APB4LPENR_SYSCFGEN           0x2
#define BF_RCC_APB4LPENR_SYSCFGEN(v)        (((v) & 0x1) << 1)
#define BFM_RCC_APB4LPENR_SYSCFGEN(v)       BM_RCC_APB4LPENR_SYSCFGEN
#define BF_RCC_APB4LPENR_SYSCFGEN_V(e)      BF_RCC_APB4LPENR_SYSCFGEN(BV_RCC_APB4LPENR_SYSCFGEN__##e)
#define BFM_RCC_APB4LPENR_SYSCFGEN_V(v)     BM_RCC_APB4LPENR_SYSCFGEN

#endif /* __HEADERGEN_RCC_H__*/