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|
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_SPI_H__
#define __HEADERGEN_SPI_H__
#include "macro.h"
#define STA_SPI1 (0x40013000)
#define STA_SPI2 (0x40003800)
#define STA_SPI3 (0x40003c00)
#define STA_SPI4 (0x40013400)
#define STA_SPI5 (0x40015000)
#define STA_SPI6 (0x58001400)
#define REG_SPI_CR1 st_reg(SPI_CR1)
#define STO_SPI_CR1 (0x0)
#define STT_SPI_CR1 STIO_32_RW
#define STN_SPI_CR1 SPI_CR1
#define BP_SPI_CR1_IO_LOCK 16
#define BM_SPI_CR1_IO_LOCK 0x10000
#define BF_SPI_CR1_IO_LOCK(v) (((v) & 0x1) << 16)
#define BFM_SPI_CR1_IO_LOCK(v) BM_SPI_CR1_IO_LOCK
#define BF_SPI_CR1_IO_LOCK_V(e) BF_SPI_CR1_IO_LOCK(BV_SPI_CR1_IO_LOCK__##e)
#define BFM_SPI_CR1_IO_LOCK_V(v) BM_SPI_CR1_IO_LOCK
#define BP_SPI_CR1_TCRCINI 15
#define BM_SPI_CR1_TCRCINI 0x8000
#define BF_SPI_CR1_TCRCINI(v) (((v) & 0x1) << 15)
#define BFM_SPI_CR1_TCRCINI(v) BM_SPI_CR1_TCRCINI
#define BF_SPI_CR1_TCRCINI_V(e) BF_SPI_CR1_TCRCINI(BV_SPI_CR1_TCRCINI__##e)
#define BFM_SPI_CR1_TCRCINI_V(v) BM_SPI_CR1_TCRCINI
#define BP_SPI_CR1_RCRCINI 14
#define BM_SPI_CR1_RCRCINI 0x4000
#define BF_SPI_CR1_RCRCINI(v) (((v) & 0x1) << 14)
#define BFM_SPI_CR1_RCRCINI(v) BM_SPI_CR1_RCRCINI
#define BF_SPI_CR1_RCRCINI_V(e) BF_SPI_CR1_RCRCINI(BV_SPI_CR1_RCRCINI__##e)
#define BFM_SPI_CR1_RCRCINI_V(v) BM_SPI_CR1_RCRCINI
#define BP_SPI_CR1_CRC33_17 13
#define BM_SPI_CR1_CRC33_17 0x2000
#define BF_SPI_CR1_CRC33_17(v) (((v) & 0x1) << 13)
#define BFM_SPI_CR1_CRC33_17(v) BM_SPI_CR1_CRC33_17
#define BF_SPI_CR1_CRC33_17_V(e) BF_SPI_CR1_CRC33_17(BV_SPI_CR1_CRC33_17__##e)
#define BFM_SPI_CR1_CRC33_17_V(v) BM_SPI_CR1_CRC33_17
#define BP_SPI_CR1_SSI 12
#define BM_SPI_CR1_SSI 0x1000
#define BF_SPI_CR1_SSI(v) (((v) & 0x1) << 12)
#define BFM_SPI_CR1_SSI(v) BM_SPI_CR1_SSI
#define BF_SPI_CR1_SSI_V(e) BF_SPI_CR1_SSI(BV_SPI_CR1_SSI__##e)
#define BFM_SPI_CR1_SSI_V(v) BM_SPI_CR1_SSI
#define BP_SPI_CR1_HDDIR 11
#define BM_SPI_CR1_HDDIR 0x800
#define BF_SPI_CR1_HDDIR(v) (((v) & 0x1) << 11)
#define BFM_SPI_CR1_HDDIR(v) BM_SPI_CR1_HDDIR
#define BF_SPI_CR1_HDDIR_V(e) BF_SPI_CR1_HDDIR(BV_SPI_CR1_HDDIR__##e)
#define BFM_SPI_CR1_HDDIR_V(v) BM_SPI_CR1_HDDIR
#define BP_SPI_CR1_CSUSP 10
#define BM_SPI_CR1_CSUSP 0x400
#define BF_SPI_CR1_CSUSP(v) (((v) & 0x1) << 10)
#define BFM_SPI_CR1_CSUSP(v) BM_SPI_CR1_CSUSP
#define BF_SPI_CR1_CSUSP_V(e) BF_SPI_CR1_CSUSP(BV_SPI_CR1_CSUSP__##e)
#define BFM_SPI_CR1_CSUSP_V(v) BM_SPI_CR1_CSUSP
#define BP_SPI_CR1_CSTART 9
#define BM_SPI_CR1_CSTART 0x200
#define BF_SPI_CR1_CSTART(v) (((v) & 0x1) << 9)
#define BFM_SPI_CR1_CSTART(v) BM_SPI_CR1_CSTART
#define BF_SPI_CR1_CSTART_V(e) BF_SPI_CR1_CSTART(BV_SPI_CR1_CSTART__##e)
#define BFM_SPI_CR1_CSTART_V(v) BM_SPI_CR1_CSTART
#define BP_SPI_CR1_MASRX 8
#define BM_SPI_CR1_MASRX 0x100
#define BF_SPI_CR1_MASRX(v) (((v) & 0x1) << 8)
#define BFM_SPI_CR1_MASRX(v) BM_SPI_CR1_MASRX
#define BF_SPI_CR1_MASRX_V(e) BF_SPI_CR1_MASRX(BV_SPI_CR1_MASRX__##e)
#define BFM_SPI_CR1_MASRX_V(v) BM_SPI_CR1_MASRX
#define BP_SPI_CR1_SPE 0
#define BM_SPI_CR1_SPE 0x1
#define BF_SPI_CR1_SPE(v) (((v) & 0x1) << 0)
#define BFM_SPI_CR1_SPE(v) BM_SPI_CR1_SPE
#define BF_SPI_CR1_SPE_V(e) BF_SPI_CR1_SPE(BV_SPI_CR1_SPE__##e)
#define BFM_SPI_CR1_SPE_V(v) BM_SPI_CR1_SPE
#define REG_SPI_CR2 st_reg(SPI_CR2)
#define STO_SPI_CR2 (0x4)
#define STT_SPI_CR2 STIO_32_RW
#define STN_SPI_CR2 SPI_CR2
#define BP_SPI_CR2_TSER 16
#define BM_SPI_CR2_TSER 0xffff0000
#define BF_SPI_CR2_TSER(v) (((v) & 0xffff) << 16)
#define BFM_SPI_CR2_TSER(v) BM_SPI_CR2_TSER
#define BF_SPI_CR2_TSER_V(e) BF_SPI_CR2_TSER(BV_SPI_CR2_TSER__##e)
#define BFM_SPI_CR2_TSER_V(v) BM_SPI_CR2_TSER
#define BP_SPI_CR2_TSIZE 0
#define BM_SPI_CR2_TSIZE 0xffff
#define BF_SPI_CR2_TSIZE(v) (((v) & 0xffff) << 0)
#define BFM_SPI_CR2_TSIZE(v) BM_SPI_CR2_TSIZE
#define BF_SPI_CR2_TSIZE_V(e) BF_SPI_CR2_TSIZE(BV_SPI_CR2_TSIZE__##e)
#define BFM_SPI_CR2_TSIZE_V(v) BM_SPI_CR2_TSIZE
#define REG_SPI_CFG1 st_reg(SPI_CFG1)
#define STO_SPI_CFG1 (0x8)
#define STT_SPI_CFG1 STIO_32_RW
#define STN_SPI_CFG1 SPI_CFG1
#define BP_SPI_CFG1_MBR 28
#define BM_SPI_CFG1_MBR 0x70000000
#define BF_SPI_CFG1_MBR(v) (((v) & 0x7) << 28)
#define BFM_SPI_CFG1_MBR(v) BM_SPI_CFG1_MBR
#define BF_SPI_CFG1_MBR_V(e) BF_SPI_CFG1_MBR(BV_SPI_CFG1_MBR__##e)
#define BFM_SPI_CFG1_MBR_V(v) BM_SPI_CFG1_MBR
#define BP_SPI_CFG1_CRCSIZE 16
#define BM_SPI_CFG1_CRCSIZE 0x1f0000
#define BF_SPI_CFG1_CRCSIZE(v) (((v) & 0x1f) << 16)
#define BFM_SPI_CFG1_CRCSIZE(v) BM_SPI_CFG1_CRCSIZE
#define BF_SPI_CFG1_CRCSIZE_V(e) BF_SPI_CFG1_CRCSIZE(BV_SPI_CFG1_CRCSIZE__##e)
#define BFM_SPI_CFG1_CRCSIZE_V(v) BM_SPI_CFG1_CRCSIZE
#define BP_SPI_CFG1_UDRDET 11
#define BM_SPI_CFG1_UDRDET 0x1800
#define BF_SPI_CFG1_UDRDET(v) (((v) & 0x3) << 11)
#define BFM_SPI_CFG1_UDRDET(v) BM_SPI_CFG1_UDRDET
#define BF_SPI_CFG1_UDRDET_V(e) BF_SPI_CFG1_UDRDET(BV_SPI_CFG1_UDRDET__##e)
#define BFM_SPI_CFG1_UDRDET_V(v) BM_SPI_CFG1_UDRDET
#define BP_SPI_CFG1_UDRCFG 9
#define BM_SPI_CFG1_UDRCFG 0x600
#define BF_SPI_CFG1_UDRCFG(v) (((v) & 0x3) << 9)
#define BFM_SPI_CFG1_UDRCFG(v) BM_SPI_CFG1_UDRCFG
#define BF_SPI_CFG1_UDRCFG_V(e) BF_SPI_CFG1_UDRCFG(BV_SPI_CFG1_UDRCFG__##e)
#define BFM_SPI_CFG1_UDRCFG_V(v) BM_SPI_CFG1_UDRCFG
#define BP_SPI_CFG1_FTHLV 5
#define BM_SPI_CFG1_FTHLV 0x1e0
#define BF_SPI_CFG1_FTHLV(v) (((v) & 0xf) << 5)
#define BFM_SPI_CFG1_FTHLV(v) BM_SPI_CFG1_FTHLV
#define BF_SPI_CFG1_FTHLV_V(e) BF_SPI_CFG1_FTHLV(BV_SPI_CFG1_FTHLV__##e)
#define BFM_SPI_CFG1_FTHLV_V(v) BM_SPI_CFG1_FTHLV
#define BP_SPI_CFG1_DSIZE 0
#define BM_SPI_CFG1_DSIZE 0x1f
#define BF_SPI_CFG1_DSIZE(v) (((v) & 0x1f) << 0)
#define BFM_SPI_CFG1_DSIZE(v) BM_SPI_CFG1_DSIZE
#define BF_SPI_CFG1_DSIZE_V(e) BF_SPI_CFG1_DSIZE(BV_SPI_CFG1_DSIZE__##e)
#define BFM_SPI_CFG1_DSIZE_V(v) BM_SPI_CFG1_DSIZE
#define BP_SPI_CFG1_CRCEN 22
#define BM_SPI_CFG1_CRCEN 0x400000
#define BF_SPI_CFG1_CRCEN(v) (((v) & 0x1) << 22)
#define BFM_SPI_CFG1_CRCEN(v) BM_SPI_CFG1_CRCEN
#define BF_SPI_CFG1_CRCEN_V(e) BF_SPI_CFG1_CRCEN(BV_SPI_CFG1_CRCEN__##e)
#define BFM_SPI_CFG1_CRCEN_V(v) BM_SPI_CFG1_CRCEN
#define BP_SPI_CFG1_TXDMAEN 15
#define BM_SPI_CFG1_TXDMAEN 0x8000
#define BF_SPI_CFG1_TXDMAEN(v) (((v) & 0x1) << 15)
#define BFM_SPI_CFG1_TXDMAEN(v) BM_SPI_CFG1_TXDMAEN
#define BF_SPI_CFG1_TXDMAEN_V(e) BF_SPI_CFG1_TXDMAEN(BV_SPI_CFG1_TXDMAEN__##e)
#define BFM_SPI_CFG1_TXDMAEN_V(v) BM_SPI_CFG1_TXDMAEN
#define BP_SPI_CFG1_RXDMAEN 14
#define BM_SPI_CFG1_RXDMAEN 0x4000
#define BF_SPI_CFG1_RXDMAEN(v) (((v) & 0x1) << 14)
#define BFM_SPI_CFG1_RXDMAEN(v) BM_SPI_CFG1_RXDMAEN
#define BF_SPI_CFG1_RXDMAEN_V(e) BF_SPI_CFG1_RXDMAEN(BV_SPI_CFG1_RXDMAEN__##e)
#define BFM_SPI_CFG1_RXDMAEN_V(v) BM_SPI_CFG1_RXDMAEN
#define REG_SPI_CFG2 st_reg(SPI_CFG2)
#define STO_SPI_CFG2 (0xc)
#define STT_SPI_CFG2 STIO_32_RW
#define STN_SPI_CFG2 SPI_CFG2
#define BP_SPI_CFG2_SP 19
#define BM_SPI_CFG2_SP 0x380000
#define BV_SPI_CFG2_SP__MOTOROLA 0x0
#define BV_SPI_CFG2_SP__TI 0x1
#define BF_SPI_CFG2_SP(v) (((v) & 0x7) << 19)
#define BFM_SPI_CFG2_SP(v) BM_SPI_CFG2_SP
#define BF_SPI_CFG2_SP_V(e) BF_SPI_CFG2_SP(BV_SPI_CFG2_SP__##e)
#define BFM_SPI_CFG2_SP_V(v) BM_SPI_CFG2_SP
#define BP_SPI_CFG2_COMM 17
#define BM_SPI_CFG2_COMM 0x60000
#define BV_SPI_CFG2_COMM__DUPLEX 0x0
#define BV_SPI_CFG2_COMM__TXONLY 0x1
#define BV_SPI_CFG2_COMM__RXONLY 0x2
#define BV_SPI_CFG2_COMM__HALF_DUPLEX 0x3
#define BF_SPI_CFG2_COMM(v) (((v) & 0x3) << 17)
#define BFM_SPI_CFG2_COMM(v) BM_SPI_CFG2_COMM
#define BF_SPI_CFG2_COMM_V(e) BF_SPI_CFG2_COMM(BV_SPI_CFG2_COMM__##e)
#define BFM_SPI_CFG2_COMM_V(v) BM_SPI_CFG2_COMM
#define BP_SPI_CFG2_MIDI 4
#define BM_SPI_CFG2_MIDI 0xf0
#define BF_SPI_CFG2_MIDI(v) (((v) & 0xf) << 4)
#define BFM_SPI_CFG2_MIDI(v) BM_SPI_CFG2_MIDI
#define BF_SPI_CFG2_MIDI_V(e) BF_SPI_CFG2_MIDI(BV_SPI_CFG2_MIDI__##e)
#define BFM_SPI_CFG2_MIDI_V(v) BM_SPI_CFG2_MIDI
#define BP_SPI_CFG2_MSSI 0
#define BM_SPI_CFG2_MSSI 0xf
#define BF_SPI_CFG2_MSSI(v) (((v) & 0xf) << 0)
#define BFM_SPI_CFG2_MSSI(v) BM_SPI_CFG2_MSSI
#define BF_SPI_CFG2_MSSI_V(e) BF_SPI_CFG2_MSSI(BV_SPI_CFG2_MSSI__##e)
#define BFM_SPI_CFG2_MSSI_V(v) BM_SPI_CFG2_MSSI
#define BP_SPI_CFG2_AFCNTR 31
#define BM_SPI_CFG2_AFCNTR 0x80000000
#define BF_SPI_CFG2_AFCNTR(v) (((v) & 0x1) << 31)
#define BFM_SPI_CFG2_AFCNTR(v) BM_SPI_CFG2_AFCNTR
#define BF_SPI_CFG2_AFCNTR_V(e) BF_SPI_CFG2_AFCNTR(BV_SPI_CFG2_AFCNTR__##e)
#define BFM_SPI_CFG2_AFCNTR_V(v) BM_SPI_CFG2_AFCNTR
#define BP_SPI_CFG2_SSOM 30
#define BM_SPI_CFG2_SSOM 0x40000000
#define BF_SPI_CFG2_SSOM(v) (((v) & 0x1) << 30)
#define BFM_SPI_CFG2_SSOM(v) BM_SPI_CFG2_SSOM
#define BF_SPI_CFG2_SSOM_V(e) BF_SPI_CFG2_SSOM(BV_SPI_CFG2_SSOM__##e)
#define BFM_SPI_CFG2_SSOM_V(v) BM_SPI_CFG2_SSOM
#define BP_SPI_CFG2_SSOE 29
#define BM_SPI_CFG2_SSOE 0x20000000
#define BF_SPI_CFG2_SSOE(v) (((v) & 0x1) << 29)
#define BFM_SPI_CFG2_SSOE(v) BM_SPI_CFG2_SSOE
#define BF_SPI_CFG2_SSOE_V(e) BF_SPI_CFG2_SSOE(BV_SPI_CFG2_SSOE__##e)
#define BFM_SPI_CFG2_SSOE_V(v) BM_SPI_CFG2_SSOE
#define BP_SPI_CFG2_SSIOP 28
#define BM_SPI_CFG2_SSIOP 0x10000000
#define BF_SPI_CFG2_SSIOP(v) (((v) & 0x1) << 28)
#define BFM_SPI_CFG2_SSIOP(v) BM_SPI_CFG2_SSIOP
#define BF_SPI_CFG2_SSIOP_V(e) BF_SPI_CFG2_SSIOP(BV_SPI_CFG2_SSIOP__##e)
#define BFM_SPI_CFG2_SSIOP_V(v) BM_SPI_CFG2_SSIOP
#define BP_SPI_CFG2_SSM 26
#define BM_SPI_CFG2_SSM 0x4000000
#define BV_SPI_CFG2_SSM__SS_PAD 0x0
#define BV_SPI_CFG2_SSM__SSI_BIT 0x1
#define BF_SPI_CFG2_SSM(v) (((v) & 0x1) << 26)
#define BFM_SPI_CFG2_SSM(v) BM_SPI_CFG2_SSM
#define BF_SPI_CFG2_SSM_V(e) BF_SPI_CFG2_SSM(BV_SPI_CFG2_SSM__##e)
#define BFM_SPI_CFG2_SSM_V(v) BM_SPI_CFG2_SSM
#define BP_SPI_CFG2_CPOL 25
#define BM_SPI_CFG2_CPOL 0x2000000
#define BF_SPI_CFG2_CPOL(v) (((v) & 0x1) << 25)
#define BFM_SPI_CFG2_CPOL(v) BM_SPI_CFG2_CPOL
#define BF_SPI_CFG2_CPOL_V(e) BF_SPI_CFG2_CPOL(BV_SPI_CFG2_CPOL__##e)
#define BFM_SPI_CFG2_CPOL_V(v) BM_SPI_CFG2_CPOL
#define BP_SPI_CFG2_CPHA 24
#define BM_SPI_CFG2_CPHA 0x1000000
#define BF_SPI_CFG2_CPHA(v) (((v) & 0x1) << 24)
#define BFM_SPI_CFG2_CPHA(v) BM_SPI_CFG2_CPHA
#define BF_SPI_CFG2_CPHA_V(e) BF_SPI_CFG2_CPHA(BV_SPI_CFG2_CPHA__##e)
#define BFM_SPI_CFG2_CPHA_V(v) BM_SPI_CFG2_CPHA
#define BP_SPI_CFG2_LSBFIRST 23
#define BM_SPI_CFG2_LSBFIRST 0x800000
#define BF_SPI_CFG2_LSBFIRST(v) (((v) & 0x1) << 23)
#define BFM_SPI_CFG2_LSBFIRST(v) BM_SPI_CFG2_LSBFIRST
#define BF_SPI_CFG2_LSBFIRST_V(e) BF_SPI_CFG2_LSBFIRST(BV_SPI_CFG2_LSBFIRST__##e)
#define BFM_SPI_CFG2_LSBFIRST_V(v) BM_SPI_CFG2_LSBFIRST
#define BP_SPI_CFG2_MASTER 22
#define BM_SPI_CFG2_MASTER 0x400000
#define BF_SPI_CFG2_MASTER(v) (((v) & 0x1) << 22)
#define BFM_SPI_CFG2_MASTER(v) BM_SPI_CFG2_MASTER
#define BF_SPI_CFG2_MASTER_V(e) BF_SPI_CFG2_MASTER(BV_SPI_CFG2_MASTER__##e)
#define BFM_SPI_CFG2_MASTER_V(v) BM_SPI_CFG2_MASTER
#define BP_SPI_CFG2_IOSWP 15
#define BM_SPI_CFG2_IOSWP 0x8000
#define BF_SPI_CFG2_IOSWP(v) (((v) & 0x1) << 15)
#define BFM_SPI_CFG2_IOSWP(v) BM_SPI_CFG2_IOSWP
#define BF_SPI_CFG2_IOSWP_V(e) BF_SPI_CFG2_IOSWP(BV_SPI_CFG2_IOSWP__##e)
#define BFM_SPI_CFG2_IOSWP_V(v) BM_SPI_CFG2_IOSWP
#define REG_SPI_IER st_reg(SPI_IER)
#define STO_SPI_IER (0x10)
#define STT_SPI_IER STIO_32_RW
#define STN_SPI_IER SPI_IER
#define BP_SPI_IER_TSERFIE 10
#define BM_SPI_IER_TSERFIE 0x400
#define BF_SPI_IER_TSERFIE(v) (((v) & 0x1) << 10)
#define BFM_SPI_IER_TSERFIE(v) BM_SPI_IER_TSERFIE
#define BF_SPI_IER_TSERFIE_V(e) BF_SPI_IER_TSERFIE(BV_SPI_IER_TSERFIE__##e)
#define BFM_SPI_IER_TSERFIE_V(v) BM_SPI_IER_TSERFIE
#define BP_SPI_IER_MODFIE 9
#define BM_SPI_IER_MODFIE 0x200
#define BF_SPI_IER_MODFIE(v) (((v) & 0x1) << 9)
#define BFM_SPI_IER_MODFIE(v) BM_SPI_IER_MODFIE
#define BF_SPI_IER_MODFIE_V(e) BF_SPI_IER_MODFIE(BV_SPI_IER_MODFIE__##e)
#define BFM_SPI_IER_MODFIE_V(v) BM_SPI_IER_MODFIE
#define BP_SPI_IER_TIFREIE 8
#define BM_SPI_IER_TIFREIE 0x100
#define BF_SPI_IER_TIFREIE(v) (((v) & 0x1) << 8)
#define BFM_SPI_IER_TIFREIE(v) BM_SPI_IER_TIFREIE
#define BF_SPI_IER_TIFREIE_V(e) BF_SPI_IER_TIFREIE(BV_SPI_IER_TIFREIE__##e)
#define BFM_SPI_IER_TIFREIE_V(v) BM_SPI_IER_TIFREIE
#define BP_SPI_IER_CRCEIE 7
#define BM_SPI_IER_CRCEIE 0x80
#define BF_SPI_IER_CRCEIE(v) (((v) & 0x1) << 7)
#define BFM_SPI_IER_CRCEIE(v) BM_SPI_IER_CRCEIE
#define BF_SPI_IER_CRCEIE_V(e) BF_SPI_IER_CRCEIE(BV_SPI_IER_CRCEIE__##e)
#define BFM_SPI_IER_CRCEIE_V(v) BM_SPI_IER_CRCEIE
#define BP_SPI_IER_OVRIE 6
#define BM_SPI_IER_OVRIE 0x40
#define BF_SPI_IER_OVRIE(v) (((v) & 0x1) << 6)
#define BFM_SPI_IER_OVRIE(v) BM_SPI_IER_OVRIE
#define BF_SPI_IER_OVRIE_V(e) BF_SPI_IER_OVRIE(BV_SPI_IER_OVRIE__##e)
#define BFM_SPI_IER_OVRIE_V(v) BM_SPI_IER_OVRIE
#define BP_SPI_IER_UDRIE 5
#define BM_SPI_IER_UDRIE 0x20
#define BF_SPI_IER_UDRIE(v) (((v) & 0x1) << 5)
#define BFM_SPI_IER_UDRIE(v) BM_SPI_IER_UDRIE
#define BF_SPI_IER_UDRIE_V(e) BF_SPI_IER_UDRIE(BV_SPI_IER_UDRIE__##e)
#define BFM_SPI_IER_UDRIE_V(v) BM_SPI_IER_UDRIE
#define BP_SPI_IER_TXTFIE 4
#define BM_SPI_IER_TXTFIE 0x10
#define BF_SPI_IER_TXTFIE(v) (((v) & 0x1) << 4)
#define BFM_SPI_IER_TXTFIE(v) BM_SPI_IER_TXTFIE
#define BF_SPI_IER_TXTFIE_V(e) BF_SPI_IER_TXTFIE(BV_SPI_IER_TXTFIE__##e)
#define BFM_SPI_IER_TXTFIE_V(v) BM_SPI_IER_TXTFIE
#define BP_SPI_IER_EOTIE 3
#define BM_SPI_IER_EOTIE 0x8
#define BF_SPI_IER_EOTIE(v) (((v) & 0x1) << 3)
#define BFM_SPI_IER_EOTIE(v) BM_SPI_IER_EOTIE
#define BF_SPI_IER_EOTIE_V(e) BF_SPI_IER_EOTIE(BV_SPI_IER_EOTIE__##e)
#define BFM_SPI_IER_EOTIE_V(v) BM_SPI_IER_EOTIE
#define BP_SPI_IER_DXPIE 2
#define BM_SPI_IER_DXPIE 0x4
#define BF_SPI_IER_DXPIE(v) (((v) & 0x1) << 2)
#define BFM_SPI_IER_DXPIE(v) BM_SPI_IER_DXPIE
#define BF_SPI_IER_DXPIE_V(e) BF_SPI_IER_DXPIE(BV_SPI_IER_DXPIE__##e)
#define BFM_SPI_IER_DXPIE_V(v) BM_SPI_IER_DXPIE
#define BP_SPI_IER_TXPIE 1
#define BM_SPI_IER_TXPIE 0x2
#define BF_SPI_IER_TXPIE(v) (((v) & 0x1) << 1)
#define BFM_SPI_IER_TXPIE(v) BM_SPI_IER_TXPIE
#define BF_SPI_IER_TXPIE_V(e) BF_SPI_IER_TXPIE(BV_SPI_IER_TXPIE__##e)
#define BFM_SPI_IER_TXPIE_V(v) BM_SPI_IER_TXPIE
#define BP_SPI_IER_RXPIE 0
#define BM_SPI_IER_RXPIE 0x1
#define BF_SPI_IER_RXPIE(v) (((v) & 0x1) << 0)
#define BFM_SPI_IER_RXPIE(v) BM_SPI_IER_RXPIE
#define BF_SPI_IER_RXPIE_V(e) BF_SPI_IER_RXPIE(BV_SPI_IER_RXPIE__##e)
#define BFM_SPI_IER_RXPIE_V(v) BM_SPI_IER_RXPIE
#define REG_SPI_SR st_reg(SPI_SR)
#define STO_SPI_SR (0x14)
#define STT_SPI_SR STIO_32_RW
#define STN_SPI_SR SPI_SR
#define BP_SPI_SR_CTSIZE 16
#define BM_SPI_SR_CTSIZE 0xffff0000
#define BF_SPI_SR_CTSIZE(v) (((v) & 0xffff) << 16)
#define BFM_SPI_SR_CTSIZE(v) BM_SPI_SR_CTSIZE
#define BF_SPI_SR_CTSIZE_V(e) BF_SPI_SR_CTSIZE(BV_SPI_SR_CTSIZE__##e)
#define BFM_SPI_SR_CTSIZE_V(v) BM_SPI_SR_CTSIZE
#define BP_SPI_SR_RXPLVL 13
#define BM_SPI_SR_RXPLVL 0x6000
#define BF_SPI_SR_RXPLVL(v) (((v) & 0x3) << 13)
#define BFM_SPI_SR_RXPLVL(v) BM_SPI_SR_RXPLVL
#define BF_SPI_SR_RXPLVL_V(e) BF_SPI_SR_RXPLVL(BV_SPI_SR_RXPLVL__##e)
#define BFM_SPI_SR_RXPLVL_V(v) BM_SPI_SR_RXPLVL
#define BP_SPI_SR_RXWNE 15
#define BM_SPI_SR_RXWNE 0x8000
#define BF_SPI_SR_RXWNE(v) (((v) & 0x1) << 15)
#define BFM_SPI_SR_RXWNE(v) BM_SPI_SR_RXWNE
#define BF_SPI_SR_RXWNE_V(e) BF_SPI_SR_RXWNE(BV_SPI_SR_RXWNE__##e)
#define BFM_SPI_SR_RXWNE_V(v) BM_SPI_SR_RXWNE
#define BP_SPI_SR_TXC 12
#define BM_SPI_SR_TXC 0x1000
#define BF_SPI_SR_TXC(v) (((v) & 0x1) << 12)
#define BFM_SPI_SR_TXC(v) BM_SPI_SR_TXC
#define BF_SPI_SR_TXC_V(e) BF_SPI_SR_TXC(BV_SPI_SR_TXC__##e)
#define BFM_SPI_SR_TXC_V(v) BM_SPI_SR_TXC
#define BP_SPI_SR_SUSP 11
#define BM_SPI_SR_SUSP 0x800
#define BF_SPI_SR_SUSP(v) (((v) & 0x1) << 11)
#define BFM_SPI_SR_SUSP(v) BM_SPI_SR_SUSP
#define BF_SPI_SR_SUSP_V(e) BF_SPI_SR_SUSP(BV_SPI_SR_SUSP__##e)
#define BFM_SPI_SR_SUSP_V(v) BM_SPI_SR_SUSP
#define BP_SPI_SR_TSERF 10
#define BM_SPI_SR_TSERF 0x400
#define BF_SPI_SR_TSERF(v) (((v) & 0x1) << 10)
#define BFM_SPI_SR_TSERF(v) BM_SPI_SR_TSERF
#define BF_SPI_SR_TSERF_V(e) BF_SPI_SR_TSERF(BV_SPI_SR_TSERF__##e)
#define BFM_SPI_SR_TSERF_V(v) BM_SPI_SR_TSERF
#define BP_SPI_SR_MODF 9
#define BM_SPI_SR_MODF 0x200
#define BF_SPI_SR_MODF(v) (((v) & 0x1) << 9)
#define BFM_SPI_SR_MODF(v) BM_SPI_SR_MODF
#define BF_SPI_SR_MODF_V(e) BF_SPI_SR_MODF(BV_SPI_SR_MODF__##e)
#define BFM_SPI_SR_MODF_V(v) BM_SPI_SR_MODF
#define BP_SPI_SR_TIFRE 8
#define BM_SPI_SR_TIFRE 0x100
#define BF_SPI_SR_TIFRE(v) (((v) & 0x1) << 8)
#define BFM_SPI_SR_TIFRE(v) BM_SPI_SR_TIFRE
#define BF_SPI_SR_TIFRE_V(e) BF_SPI_SR_TIFRE(BV_SPI_SR_TIFRE__##e)
#define BFM_SPI_SR_TIFRE_V(v) BM_SPI_SR_TIFRE
#define BP_SPI_SR_CRCE 7
#define BM_SPI_SR_CRCE 0x80
#define BF_SPI_SR_CRCE(v) (((v) & 0x1) << 7)
#define BFM_SPI_SR_CRCE(v) BM_SPI_SR_CRCE
#define BF_SPI_SR_CRCE_V(e) BF_SPI_SR_CRCE(BV_SPI_SR_CRCE__##e)
#define BFM_SPI_SR_CRCE_V(v) BM_SPI_SR_CRCE
#define BP_SPI_SR_OVR 6
#define BM_SPI_SR_OVR 0x40
#define BF_SPI_SR_OVR(v) (((v) & 0x1) << 6)
#define BFM_SPI_SR_OVR(v) BM_SPI_SR_OVR
#define BF_SPI_SR_OVR_V(e) BF_SPI_SR_OVR(BV_SPI_SR_OVR__##e)
#define BFM_SPI_SR_OVR_V(v) BM_SPI_SR_OVR
#define BP_SPI_SR_UDR 5
#define BM_SPI_SR_UDR 0x20
#define BF_SPI_SR_UDR(v) (((v) & 0x1) << 5)
#define BFM_SPI_SR_UDR(v) BM_SPI_SR_UDR
#define BF_SPI_SR_UDR_V(e) BF_SPI_SR_UDR(BV_SPI_SR_UDR__##e)
#define BFM_SPI_SR_UDR_V(v) BM_SPI_SR_UDR
#define BP_SPI_SR_TXTF 4
#define BM_SPI_SR_TXTF 0x10
#define BF_SPI_SR_TXTF(v) (((v) & 0x1) << 4)
#define BFM_SPI_SR_TXTF(v) BM_SPI_SR_TXTF
#define BF_SPI_SR_TXTF_V(e) BF_SPI_SR_TXTF(BV_SPI_SR_TXTF__##e)
#define BFM_SPI_SR_TXTF_V(v) BM_SPI_SR_TXTF
#define BP_SPI_SR_EOT 3
#define BM_SPI_SR_EOT 0x8
#define BF_SPI_SR_EOT(v) (((v) & 0x1) << 3)
#define BFM_SPI_SR_EOT(v) BM_SPI_SR_EOT
#define BF_SPI_SR_EOT_V(e) BF_SPI_SR_EOT(BV_SPI_SR_EOT__##e)
#define BFM_SPI_SR_EOT_V(v) BM_SPI_SR_EOT
#define BP_SPI_SR_DXP 2
#define BM_SPI_SR_DXP 0x4
#define BF_SPI_SR_DXP(v) (((v) & 0x1) << 2)
#define BFM_SPI_SR_DXP(v) BM_SPI_SR_DXP
#define BF_SPI_SR_DXP_V(e) BF_SPI_SR_DXP(BV_SPI_SR_DXP__##e)
#define BFM_SPI_SR_DXP_V(v) BM_SPI_SR_DXP
#define BP_SPI_SR_TXP 1
#define BM_SPI_SR_TXP 0x2
#define BF_SPI_SR_TXP(v) (((v) & 0x1) << 1)
#define BFM_SPI_SR_TXP(v) BM_SPI_SR_TXP
#define BF_SPI_SR_TXP_V(e) BF_SPI_SR_TXP(BV_SPI_SR_TXP__##e)
#define BFM_SPI_SR_TXP_V(v) BM_SPI_SR_TXP
#define BP_SPI_SR_RXP 0
#define BM_SPI_SR_RXP 0x1
#define BF_SPI_SR_RXP(v) (((v) & 0x1) << 0)
#define BFM_SPI_SR_RXP(v) BM_SPI_SR_RXP
#define BF_SPI_SR_RXP_V(e) BF_SPI_SR_RXP(BV_SPI_SR_RXP__##e)
#define BFM_SPI_SR_RXP_V(v) BM_SPI_SR_RXP
#define REG_SPI_IFCR st_reg(SPI_IFCR)
#define STO_SPI_IFCR (0x18)
#define STT_SPI_IFCR STIO_32_RW
#define STN_SPI_IFCR SPI_IFCR
#define BP_SPI_IFCR_SUSPC 11
#define BM_SPI_IFCR_SUSPC 0x800
#define BF_SPI_IFCR_SUSPC(v) (((v) & 0x1) << 11)
#define BFM_SPI_IFCR_SUSPC(v) BM_SPI_IFCR_SUSPC
#define BF_SPI_IFCR_SUSPC_V(e) BF_SPI_IFCR_SUSPC(BV_SPI_IFCR_SUSPC__##e)
#define BFM_SPI_IFCR_SUSPC_V(v) BM_SPI_IFCR_SUSPC
#define BP_SPI_IFCR_TSERFC 10
#define BM_SPI_IFCR_TSERFC 0x400
#define BF_SPI_IFCR_TSERFC(v) (((v) & 0x1) << 10)
#define BFM_SPI_IFCR_TSERFC(v) BM_SPI_IFCR_TSERFC
#define BF_SPI_IFCR_TSERFC_V(e) BF_SPI_IFCR_TSERFC(BV_SPI_IFCR_TSERFC__##e)
#define BFM_SPI_IFCR_TSERFC_V(v) BM_SPI_IFCR_TSERFC
#define BP_SPI_IFCR_MODFC 9
#define BM_SPI_IFCR_MODFC 0x200
#define BF_SPI_IFCR_MODFC(v) (((v) & 0x1) << 9)
#define BFM_SPI_IFCR_MODFC(v) BM_SPI_IFCR_MODFC
#define BF_SPI_IFCR_MODFC_V(e) BF_SPI_IFCR_MODFC(BV_SPI_IFCR_MODFC__##e)
#define BFM_SPI_IFCR_MODFC_V(v) BM_SPI_IFCR_MODFC
#define BP_SPI_IFCR_TIFREC 8
#define BM_SPI_IFCR_TIFREC 0x100
#define BF_SPI_IFCR_TIFREC(v) (((v) & 0x1) << 8)
#define BFM_SPI_IFCR_TIFREC(v) BM_SPI_IFCR_TIFREC
#define BF_SPI_IFCR_TIFREC_V(e) BF_SPI_IFCR_TIFREC(BV_SPI_IFCR_TIFREC__##e)
#define BFM_SPI_IFCR_TIFREC_V(v) BM_SPI_IFCR_TIFREC
#define BP_SPI_IFCR_CRCEC 7
#define BM_SPI_IFCR_CRCEC 0x80
#define BF_SPI_IFCR_CRCEC(v) (((v) & 0x1) << 7)
#define BFM_SPI_IFCR_CRCEC(v) BM_SPI_IFCR_CRCEC
#define BF_SPI_IFCR_CRCEC_V(e) BF_SPI_IFCR_CRCEC(BV_SPI_IFCR_CRCEC__##e)
#define BFM_SPI_IFCR_CRCEC_V(v) BM_SPI_IFCR_CRCEC
#define BP_SPI_IFCR_OVRC 6
#define BM_SPI_IFCR_OVRC 0x40
#define BF_SPI_IFCR_OVRC(v) (((v) & 0x1) << 6)
#define BFM_SPI_IFCR_OVRC(v) BM_SPI_IFCR_OVRC
#define BF_SPI_IFCR_OVRC_V(e) BF_SPI_IFCR_OVRC(BV_SPI_IFCR_OVRC__##e)
#define BFM_SPI_IFCR_OVRC_V(v) BM_SPI_IFCR_OVRC
#define BP_SPI_IFCR_UDRC 5
#define BM_SPI_IFCR_UDRC 0x20
#define BF_SPI_IFCR_UDRC(v) (((v) & 0x1) << 5)
#define BFM_SPI_IFCR_UDRC(v) BM_SPI_IFCR_UDRC
#define BF_SPI_IFCR_UDRC_V(e) BF_SPI_IFCR_UDRC(BV_SPI_IFCR_UDRC__##e)
#define BFM_SPI_IFCR_UDRC_V(v) BM_SPI_IFCR_UDRC
#define BP_SPI_IFCR_TXTFC 4
#define BM_SPI_IFCR_TXTFC 0x10
#define BF_SPI_IFCR_TXTFC(v) (((v) & 0x1) << 4)
#define BFM_SPI_IFCR_TXTFC(v) BM_SPI_IFCR_TXTFC
#define BF_SPI_IFCR_TXTFC_V(e) BF_SPI_IFCR_TXTFC(BV_SPI_IFCR_TXTFC__##e)
#define BFM_SPI_IFCR_TXTFC_V(v) BM_SPI_IFCR_TXTFC
#define BP_SPI_IFCR_EOTC 3
#define BM_SPI_IFCR_EOTC 0x8
#define BF_SPI_IFCR_EOTC(v) (((v) & 0x1) << 3)
#define BFM_SPI_IFCR_EOTC(v) BM_SPI_IFCR_EOTC
#define BF_SPI_IFCR_EOTC_V(e) BF_SPI_IFCR_EOTC(BV_SPI_IFCR_EOTC__##e)
#define BFM_SPI_IFCR_EOTC_V(v) BM_SPI_IFCR_EOTC
#define REG_SPI_TXDR8 st_reg(SPI_TXDR8)
#define STO_SPI_TXDR8 (0x20)
#define STT_SPI_TXDR8 STIO_8_RW
#define STN_SPI_TXDR8 SPI_TXDR8
#define REG_SPI_TXDR16 st_reg(SPI_TXDR16)
#define STO_SPI_TXDR16 (0x20)
#define STT_SPI_TXDR16 STIO_16_RW
#define STN_SPI_TXDR16 SPI_TXDR16
#define REG_SPI_TXDR32 st_reg(SPI_TXDR32)
#define STO_SPI_TXDR32 (0x20)
#define STT_SPI_TXDR32 STIO_32_RW
#define STN_SPI_TXDR32 SPI_TXDR32
#define REG_SPI_RXDR8 st_reg(SPI_RXDR8)
#define STO_SPI_RXDR8 (0x30)
#define STT_SPI_RXDR8 STIO_8_RW
#define STN_SPI_RXDR8 SPI_RXDR8
#define REG_SPI_RXDR16 st_reg(SPI_RXDR16)
#define STO_SPI_RXDR16 (0x30)
#define STT_SPI_RXDR16 STIO_16_RW
#define STN_SPI_RXDR16 SPI_RXDR16
#define REG_SPI_RXDR32 st_reg(SPI_RXDR32)
#define STO_SPI_RXDR32 (0x30)
#define STT_SPI_RXDR32 STIO_32_RW
#define STN_SPI_RXDR32 SPI_RXDR32
#define REG_SPI_CRCPOLY st_reg(SPI_CRCPOLY)
#define STO_SPI_CRCPOLY (0x40)
#define STT_SPI_CRCPOLY STIO_32_RW
#define STN_SPI_CRCPOLY SPI_CRCPOLY
#define REG_SPI_TXCRC st_reg(SPI_TXCRC)
#define STO_SPI_TXCRC (0x44)
#define STT_SPI_TXCRC STIO_32_RW
#define STN_SPI_TXCRC SPI_TXCRC
#define REG_SPI_RXCRC st_reg(SPI_RXCRC)
#define STO_SPI_RXCRC (0x48)
#define STT_SPI_RXCRC STIO_32_RW
#define STN_SPI_RXCRC SPI_RXCRC
#define REG_SPI_UDRDR st_reg(SPI_UDRDR)
#define STO_SPI_UDRDR (0x4c)
#define STT_SPI_UDRDR STIO_32_RW
#define STN_SPI_UDRDR SPI_UDRDR
#define REG_SPI_I2SCFGR st_reg(SPI_I2SCFGR)
#define STO_SPI_I2SCFGR (0x50)
#define STT_SPI_I2SCFGR STIO_32_RW
#define STN_SPI_I2SCFGR SPI_I2SCFGR
#define BP_SPI_I2SCFGR_I2SDIV 16
#define BM_SPI_I2SCFGR_I2SDIV 0xff0000
#define BF_SPI_I2SCFGR_I2SDIV(v) (((v) & 0xff) << 16)
#define BFM_SPI_I2SCFGR_I2SDIV(v) BM_SPI_I2SCFGR_I2SDIV
#define BF_SPI_I2SCFGR_I2SDIV_V(e) BF_SPI_I2SCFGR_I2SDIV(BV_SPI_I2SCFGR_I2SDIV__##e)
#define BFM_SPI_I2SCFGR_I2SDIV_V(v) BM_SPI_I2SCFGR_I2SDIV
#define BP_SPI_I2SCFGR_DATLEN 8
#define BM_SPI_I2SCFGR_DATLEN 0x300
#define BV_SPI_I2SCFGR_DATLEN__16BIT 0x0
#define BV_SPI_I2SCFGR_DATLEN__24BIT 0x1
#define BV_SPI_I2SCFGR_DATLEN__32BIT 0x2
#define BF_SPI_I2SCFGR_DATLEN(v) (((v) & 0x3) << 8)
#define BFM_SPI_I2SCFGR_DATLEN(v) BM_SPI_I2SCFGR_DATLEN
#define BF_SPI_I2SCFGR_DATLEN_V(e) BF_SPI_I2SCFGR_DATLEN(BV_SPI_I2SCFGR_DATLEN__##e)
#define BFM_SPI_I2SCFGR_DATLEN_V(v) BM_SPI_I2SCFGR_DATLEN
#define BP_SPI_I2SCFGR_I2SSTD 4
#define BM_SPI_I2SCFGR_I2SSTD 0x30
#define BV_SPI_I2SCFGR_I2SSTD__I2S 0x0
#define BV_SPI_I2SCFGR_I2SSTD__MSB_JUSTIFIED 0x1
#define BV_SPI_I2SCFGR_I2SSTD__LSB_JUSTIFIED 0x2
#define BV_SPI_I2SCFGR_I2SSTD__PCM 0x3
#define BF_SPI_I2SCFGR_I2SSTD(v) (((v) & 0x3) << 4)
#define BFM_SPI_I2SCFGR_I2SSTD(v) BM_SPI_I2SCFGR_I2SSTD
#define BF_SPI_I2SCFGR_I2SSTD_V(e) BF_SPI_I2SCFGR_I2SSTD(BV_SPI_I2SCFGR_I2SSTD__##e)
#define BFM_SPI_I2SCFGR_I2SSTD_V(v) BM_SPI_I2SCFGR_I2SSTD
#define BP_SPI_I2SCFGR_I2SCFG 1
#define BM_SPI_I2SCFGR_I2SCFG 0xe
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_TX 0x0
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_RX 0x1
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_TX 0x2
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_RX 0x3
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_DUPLEX 0x4
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_DUPLEX 0x5
#define BF_SPI_I2SCFGR_I2SCFG(v) (((v) & 0x7) << 1)
#define BFM_SPI_I2SCFGR_I2SCFG(v) BM_SPI_I2SCFGR_I2SCFG
#define BF_SPI_I2SCFGR_I2SCFG_V(e) BF_SPI_I2SCFGR_I2SCFG(BV_SPI_I2SCFGR_I2SCFG__##e)
#define BFM_SPI_I2SCFGR_I2SCFG_V(v) BM_SPI_I2SCFGR_I2SCFG
#define BP_SPI_I2SCFGR_MCKOE 25
#define BM_SPI_I2SCFGR_MCKOE 0x2000000
#define BF_SPI_I2SCFGR_MCKOE(v) (((v) & 0x1) << 25)
#define BFM_SPI_I2SCFGR_MCKOE(v) BM_SPI_I2SCFGR_MCKOE
#define BF_SPI_I2SCFGR_MCKOE_V(e) BF_SPI_I2SCFGR_MCKOE(BV_SPI_I2SCFGR_MCKOE__##e)
#define BFM_SPI_I2SCFGR_MCKOE_V(v) BM_SPI_I2SCFGR_MCKOE
#define BP_SPI_I2SCFGR_ODD 24
#define BM_SPI_I2SCFGR_ODD 0x1000000
#define BF_SPI_I2SCFGR_ODD(v) (((v) & 0x1) << 24)
#define BFM_SPI_I2SCFGR_ODD(v) BM_SPI_I2SCFGR_ODD
#define BF_SPI_I2SCFGR_ODD_V(e) BF_SPI_I2SCFGR_ODD(BV_SPI_I2SCFGR_ODD__##e)
#define BFM_SPI_I2SCFGR_ODD_V(v) BM_SPI_I2SCFGR_ODD
#define BP_SPI_I2SCFGR_DATFMT 14
#define BM_SPI_I2SCFGR_DATFMT 0x4000
#define BV_SPI_I2SCFGR_DATFMT__RIGHT_ALIGNED 0x0
#define BV_SPI_I2SCFGR_DATFMT__LEFT_ALIGNED 0x1
#define BF_SPI_I2SCFGR_DATFMT(v) (((v) & 0x1) << 14)
#define BFM_SPI_I2SCFGR_DATFMT(v) BM_SPI_I2SCFGR_DATFMT
#define BF_SPI_I2SCFGR_DATFMT_V(e) BF_SPI_I2SCFGR_DATFMT(BV_SPI_I2SCFGR_DATFMT__##e)
#define BFM_SPI_I2SCFGR_DATFMT_V(v) BM_SPI_I2SCFGR_DATFMT
#define BP_SPI_I2SCFGR_WSINV 13
#define BM_SPI_I2SCFGR_WSINV 0x2000
#define BF_SPI_I2SCFGR_WSINV(v) (((v) & 0x1) << 13)
#define BFM_SPI_I2SCFGR_WSINV(v) BM_SPI_I2SCFGR_WSINV
#define BF_SPI_I2SCFGR_WSINV_V(e) BF_SPI_I2SCFGR_WSINV(BV_SPI_I2SCFGR_WSINV__##e)
#define BFM_SPI_I2SCFGR_WSINV_V(v) BM_SPI_I2SCFGR_WSINV
#define BP_SPI_I2SCFGR_FIXCH 12
#define BM_SPI_I2SCFGR_FIXCH 0x1000
#define BF_SPI_I2SCFGR_FIXCH(v) (((v) & 0x1) << 12)
#define BFM_SPI_I2SCFGR_FIXCH(v) BM_SPI_I2SCFGR_FIXCH
#define BF_SPI_I2SCFGR_FIXCH_V(e) BF_SPI_I2SCFGR_FIXCH(BV_SPI_I2SCFGR_FIXCH__##e)
#define BFM_SPI_I2SCFGR_FIXCH_V(v) BM_SPI_I2SCFGR_FIXCH
#define BP_SPI_I2SCFGR_CKPOL 11
#define BM_SPI_I2SCFGR_CKPOL 0x800
#define BF_SPI_I2SCFGR_CKPOL(v) (((v) & 0x1) << 11)
#define BFM_SPI_I2SCFGR_CKPOL(v) BM_SPI_I2SCFGR_CKPOL
#define BF_SPI_I2SCFGR_CKPOL_V(e) BF_SPI_I2SCFGR_CKPOL(BV_SPI_I2SCFGR_CKPOL__##e)
#define BFM_SPI_I2SCFGR_CKPOL_V(v) BM_SPI_I2SCFGR_CKPOL
#define BP_SPI_I2SCFGR_CHLEN 10
#define BM_SPI_I2SCFGR_CHLEN 0x400
#define BV_SPI_I2SCFGR_CHLEN__16BIT 0x0
#define BV_SPI_I2SCFGR_CHLEN__32BIT 0x1
#define BF_SPI_I2SCFGR_CHLEN(v) (((v) & 0x1) << 10)
#define BFM_SPI_I2SCFGR_CHLEN(v) BM_SPI_I2SCFGR_CHLEN
#define BF_SPI_I2SCFGR_CHLEN_V(e) BF_SPI_I2SCFGR_CHLEN(BV_SPI_I2SCFGR_CHLEN__##e)
#define BFM_SPI_I2SCFGR_CHLEN_V(v) BM_SPI_I2SCFGR_CHLEN
#define BP_SPI_I2SCFGR_PCMSYNC 7
#define BM_SPI_I2SCFGR_PCMSYNC 0x80
#define BV_SPI_I2SCFGR_PCMSYNC__SHORT 0x0
#define BV_SPI_I2SCFGR_PCMSYNC__LONG 0x1
#define BF_SPI_I2SCFGR_PCMSYNC(v) (((v) & 0x1) << 7)
#define BFM_SPI_I2SCFGR_PCMSYNC(v) BM_SPI_I2SCFGR_PCMSYNC
#define BF_SPI_I2SCFGR_PCMSYNC_V(e) BF_SPI_I2SCFGR_PCMSYNC(BV_SPI_I2SCFGR_PCMSYNC__##e)
#define BFM_SPI_I2SCFGR_PCMSYNC_V(v) BM_SPI_I2SCFGR_PCMSYNC
#define BP_SPI_I2SCFGR_I2SMOD 0
#define BM_SPI_I2SCFGR_I2SMOD 0x1
#define BF_SPI_I2SCFGR_I2SMOD(v) (((v) & 0x1) << 0)
#define BFM_SPI_I2SCFGR_I2SMOD(v) BM_SPI_I2SCFGR_I2SMOD
#define BF_SPI_I2SCFGR_I2SMOD_V(e) BF_SPI_I2SCFGR_I2SMOD(BV_SPI_I2SCFGR_I2SMOD__##e)
#define BFM_SPI_I2SCFGR_I2SMOD_V(v) BM_SPI_I2SCFGR_I2SMOD
#endif /* __HEADERGEN_SPI_H__*/
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