summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/system-pp502x.c
blob: 1f2d27a7b7de0cd21ce6dbfb21839daa5f543cb7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * $Id$
 *
 * Copyright (C) 2002 by Alan Korr
 *
 * All files in this archive are subject to the GNU General Public License.
 * See the file COPYING in the source tree root for full license agreement.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#include "system.h"
#include "thread.h"

unsigned int ipod_hw_rev;

#if NUM_CORES > 1
struct mutex boostctrl_mtx NOCACHEBSS_ATTR;
#endif

#ifndef BOOTLOADER
extern void TIMER1(void);
extern void TIMER2(void);

#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
extern void ipod_mini_button_int(void);

void irq(void)
{
    if(CURRENT_CORE == CPU)
    {
        if (CPU_INT_STAT & TIMER1_MASK)
            TIMER1();
        else if (CPU_INT_STAT & TIMER2_MASK)
            TIMER2();
        else if (CPU_HI_INT_STAT & GPIO_MASK)
            ipod_mini_button_int();
    } else {
        if (COP_INT_STAT & TIMER1_MASK)
            TIMER1();
        else if (COP_INT_STAT & TIMER2_MASK)
            TIMER2();
        else if (COP_HI_INT_STAT & GPIO_MASK)
            ipod_mini_button_int();
    }
}
#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
    || (defined SANSA_E200)
/* TODO: this should really be in the target tree, but moving it there caused
   crt0.S not to find it while linking */
/* TODO: Even if it isn't in the target tree, this should be the default case */
extern void button_int(void);
extern void clickwheel_int(void);

void irq(void)
{
    if(CURRENT_CORE == CPU) {
        if (CPU_INT_STAT & TIMER1_MASK) {
#ifdef SANSA_E200
            if (GPIOF_INT_STAT & 0xff)
                button_int();
            if (GPIOH_INT_STAT & 0xc0)
                clickwheel_int();
#endif
            TIMER1();
        }
        else if (CPU_INT_STAT & TIMER2_MASK)
            TIMER2();
    } else {
        if (COP_INT_STAT & TIMER1_MASK)
            TIMER1();
        else if (COP_INT_STAT & TIMER2_MASK)
            TIMER2();
    }
}
#else
extern void ipod_4g_button_int(void);

void irq(void)
{
    if(CURRENT_CORE == CPU)
    {
        if (CPU_INT_STAT & TIMER1_MASK)
            TIMER1();
        else if (CPU_INT_STAT & TIMER2_MASK)
            TIMER2();
        else if (CPU_HI_INT_STAT & I2C_MASK)
            ipod_4g_button_int();
    } else {
        if (COP_INT_STAT & TIMER1_MASK)
            TIMER1();
        else if (COP_INT_STAT & TIMER2_MASK)
            TIMER2();
        else if (COP_HI_INT_STAT & I2C_MASK)
            ipod_4g_button_int();
    }
}
#endif
#endif /* BOOTLOADER */

/* TODO: The following two function have been lifted straight from IPL, and
   hence have a lot of numeric addresses used straight. I'd like to use
   #defines for these, but don't know what most of them are for or even what
   they should be named. Because of this I also have no way of knowing how
   to extend the funtions to do alternate cache configurations and/or
   some other CPU frequency scaling. */

#ifndef BOOTLOADER
static void ipod_init_cache(void)
{
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
    unsigned i;

    /* cache init mode? */
    CACHE_CTL = CACHE_INIT;

    /* PP5002 has 8KB cache */
    for (i = 0xf0004000; i < 0xf0006000; i += 16) {
        outl(0x0, i);
    }

    outl(0x0, 0xf000f040);
    outl(0x3fc0, 0xf000f044);

    /* enable cache */
    CACHE_CTL = CACHE_ENABLE;

    for (i = 0x10000000; i < 0x10002000; i += 16)
        inb(i);
}
#endif

/* Not all iPod targets support CPU freq. boosting yet */
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
void set_cpu_frequency(long frequency)
{
    unsigned long postmult;

# if NUM_CORES > 1
    /* Using mutex or spinlock isn't safe here. */
    while (test_and_set(&boostctrl_mtx.locked, 1)) ;
# endif
    
    if (frequency == CPUFREQ_NORMAL)
        postmult = CPUFREQ_NORMAL_MULT;
    else if (frequency == CPUFREQ_MAX)
        postmult = CPUFREQ_MAX_MULT;
    else
        postmult = CPUFREQ_DEFAULT_MULT;
    cpu_frequency = frequency;

    /* Enable PLL? */
    outl(inl(0x70000020) | (1<<30), 0x70000020);
    
    /* Select 24MHz crystal as clock source? */
    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
    
    /* Clock frequency = (24/8)*postmult */
    outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
    
    /* Wait for PLL relock? */
    udelay(2000);
    
    /* Select PLL as clock source? */
    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
    
# if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
    /* We don't know why the timer interrupt gets disabled on the PP5020
     based ipods, but without the following line, the 4Gs will freeze
     when CPU frequency changing is enabled.

     Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
     elsewhere to enable interrupts) doesn't work, we need "|=".

     It's not needed on the PP5021 and PP5022 ipods.
     */

    /* unmask interrupt source */
    CPU_INT_EN |= TIMER1_MASK;
    COP_INT_EN |= TIMER1_MASK;
# endif
    
# if NUM_CORES > 1
    boostctrl_mtx.locked = 0;
# endif
}
#elif !defined(BOOTLOADER)
void ipod_set_cpu_frequency(void)
{
    /* Enable PLL? */
    outl(inl(0x70000020) | (1<<30), 0x70000020);

    /* Select 24MHz crystal as clock source? */
    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);

    /* Clock frequency = (24/8)*25 = 75MHz */
    outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
    /* Wait for PLL relock? */
    udelay(2000);

    /* Select PLL as clock source? */
    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
}
#endif

void system_init(void)
{
#ifndef BOOTLOADER
    if (CURRENT_CORE == CPU)
    {
#ifdef SANSA_E200
        /* Reset all devices */
        DEV_RS = 0x3bfffef8;
        outl(0xffffffff, 0x60006008);
        DEV_RS = 0;
        outl(0x00000000, 0x60006008);
#endif
        /* Remap the flash ROM from 0x00000000 to 0x20000000. */
        MMAP3_LOGICAL  = 0x20000000 | 0x3a00;
        MMAP3_PHYSICAL = 0x00000000 | 0x3f84;

        /* The hw revision is written to the last 4 bytes of SDRAM by the
           bootloader - we save it before Rockbox overwrites it. */
        ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));

        /* disable all irqs */
        COP_HI_INT_CLR      = -1;
        CPU_HI_INT_CLR      = -1;
        HI_INT_FORCED_CLR   = -1;
        
        COP_INT_CLR         = -1;
        CPU_INT_CLR         = -1;
        INT_FORCED_CLR      = -1;

        GPIOA_INT_EN        = 0;
        GPIOB_INT_EN        = 0;
        GPIOC_INT_EN        = 0;
        GPIOD_INT_EN        = 0;
        GPIOE_INT_EN        = 0;
        GPIOF_INT_EN        = 0;
        GPIOG_INT_EN        = 0;
        GPIOH_INT_EN        = 0;
        GPIOI_INT_EN        = 0;
        GPIOJ_INT_EN        = 0;
        GPIOK_INT_EN        = 0;
        GPIOL_INT_EN        = 0;

# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
        spinlock_init(&boostctrl_mtx);
# endif
        
#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
        ipod_set_cpu_frequency();
#endif
    }
#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
    else
    {
        ipod_set_cpu_frequency();
    }
#endif
    ipod_init_cache();
#endif
}

void system_reboot(void)
{
    /* Reboot */
    DEV_RS |= DEV_SYSTEM;
}

int system_memory_guard(int newmode)
{
    (void)newmode;
    return 0;
}