1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
|
/*
* SPI interface driver for the DM320 SoC
*
* Copyright (C) 2007 shirour <mrobefan@gmail.com>
* Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "kernel.h"
#include "system.h"
#include "spi.h"
#define GIO_TS_ENABLE (1<<2)
#define GIO_RTC_ENABLE (1<<12)
#define GIO_BL_ENABLE (1<<13)
struct mutex spi_mtx;
struct SPI_info {
volatile unsigned short *setreg;
volatile unsigned short *clrreg;
int bit;
};
#define reg(a) ((volatile unsigned short *)(PHY_IO_BASE+a))
struct SPI_info spi_targets[] =
{
[SPI_target_TSC2100] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, GIO_TS_ENABLE },
[SPI_target_RX5X348AB] = { &IO_GIO_BITSET0, &IO_GIO_BITCLR0, GIO_RTC_ENABLE },
[SPI_target_BACKLIGHT] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, GIO_BL_ENABLE },
};
static void spi_disable_all_targets(void)
{
int i;
for(i=0;i<SPI_MAX_TARGETS;i++)
{
*spi_targets[i].clrreg = spi_targets[i].bit;
}
}
int spi_block_transfer(enum SPI_target target,
const uint8_t *tx_bytes, unsigned int tx_size,
uint8_t *rx_bytes, unsigned int rx_size)
{
mutex_lock(&spi_mtx);
/* Activate the slave select pin */
*spi_targets[target].setreg = spi_targets[target].bit;
while (tx_size--)
{
/* Send one byte */
IO_SERIAL0_TX_DATA = *tx_bytes++;
/* Wait until transfer finished */
while (IO_SERIAL0_RX_DATA & 0x100);
}
while (rx_size--)
{
/* Make the clock tick */
IO_SERIAL0_TX_DATA = 0;
/* Wait until transfer finished */
unsigned short data;
while ((data = IO_SERIAL0_RX_DATA) & 0x100);
*rx_bytes++ = data & 0xff;
}
*spi_targets[target].clrreg = spi_targets[target].bit;
mutex_unlock(&spi_mtx);
return 0;
}
void spi_init(void)
{
mutex_init(&spi_mtx);
/* Set SCLK idle level = 0 */
IO_SERIAL0_MODE |= 1<<10;
/* Enable TX */
IO_SERIAL0_TX_ENABLE = 0x0001;
/* Set GIO 18 to output for touch screen slave enable */
IO_GIO_DIR1 &= ~GIO_TS_ENABLE;
/* Set GIO 12 to output for rtc slave enable */
IO_GIO_DIR0 &= ~GIO_RTC_ENABLE;
spi_disable_all_targets(); /* make sure only one is ever enabled at a time */
}
|
